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From:   Avi Fishman <avifishman70@gmail.com>
Date:   Tue, 22 Mar 2022 19:18:34 +0200
Message-ID: <CAKKbWA4quvDbHWBdckAsKe65fDXXe8M-9CsjaP=4wsA=-NnULA@mail.gmail.com>
Subject: Re: [PATCH v3 08/11] i2c: npcm: Correct register access width
To:     =?UTF-8?Q?Jonathan_Neusch=C3=A4fer?= <j.neuschaefer@gmx.net>
Cc:     Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
        Tali Perry <tali.perry1@gmail.com>,
        Tomer Maimon <tmaimon77@gmail.com>,
        devicetree <devicetree@vger.kernel.org>,
        yangyicong@hisilicon.com, Linux I2C <linux-i2c@vger.kernel.org>,
        Benjamin Fair <benjaminfair@google.com>,
        Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
        OpenBMC Maillist <openbmc@lists.ozlabs.org>,
        JJLIU0@nuvoton.com, Lukas Bulwahn <lukas.bulwahn@gmail.com>,
        Tomer Maimon <tomer.maimon@nuvoton.com>, KWLIU@nuvoton.com,
        bence98@sch.bme.hu, Arnd Bergmann <arnd@arndb.de>,
        sven@svenpeter.dev, Rob Herring <robh+dt@kernel.org>,
        Avi Fishman <Avi.Fishman@nuvoton.com>,
        Tyrone Ting <warp5tw@gmail.com>, semen.protsenko@linaro.org,
        jie.deng@intel.com, Patrick Venture <venture@google.com>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        Wolfram Sang <wsa@kernel.org>, kfting@nuvoton.com,
        Tali Perry <tali.perry@nuvoton.com>, olof@lixom.net
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On Fri, Mar 4, 2022 at 10:42 PM Jonathan Neusch=C3=A4fer
<j.neuschaefer@gmx.net> wrote:
>
> Hello,
>
> On Thu, Mar 03, 2022 at 04:15:18PM +0200, Andy Shevchenko wrote:
> > On Thu, Mar 03, 2022 at 02:54:27PM +0200, Tali Perry wrote:
> > > > On Thu, Mar 03, 2022 at 04:31:38PM +0800, Tyrone Ting wrote:
> > > > > From: Tyrone Ting <kfting@nuvoton.com>
> > > > >
> > > > > Use ioread8 instead of ioread32 to access the SMBnCTL3 register s=
ince
> > > > > the register is only 8-bit wide.
> > > >
> > > > > Fixes: 56a1485b102e ("i2c: npcm7xx: Add Nuvoton NPCM I2C controll=
er driver")
> > > >
> > > > No, this is bad commit message, since you have bitwise masks and th=
ere is
> > > > nothing to fix from functional point of view. So, why is this a fix=
?
> > > >
> > >
> > > The next gen of this device is a 64 bit cpu.
> > > The module is and was 8 bit.
> > >
> > > The ioread32 that seemed to work smoothly on a 32 bit machine
> > > was causing a panic on a 64 bit machine.
> > > since the module is 8 bit we changed to ioread8.
> > > This is working both for the 32 and 64 CPUs with no issue.
> >
> > Then the commit message is completely wrong here.
>
> I disagree: The commit message is perhaps incomplete, but not wrong.
> The SMBnCTL3 register was specified as 8 bits wide in the datasheets of
> multiple chip generations, as far as I can tell, but the driver wrongly
> made a 32-bit access, which just happened not to blow up.
>
> So, indeed, "since the register is only 8-bit wide" seems to be a
> correct claim.
>
> > And provide necessary (no need to have noisy commit messages)
> > bits of the oops to show what's going on
>
> I guess it's blowing up now because SMBnCTL3 isn't 32-bit aligned
> (being at offset 0x0e in the controller).
>

Hi Andy,
After this clarification can you please acknowledge this specific patch?
If you think there is a better way to describe this, can you propose one?

>
> Jonathan


--=20
Regards,
Avi