Received: by 2002:a05:6a10:2726:0:0:0:0 with SMTP id ib38csp1284223pxb; Thu, 24 Mar 2022 16:53:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzey+RiHC0gxPxQJAIf+E4knCtpn7Rhrs8QItUYZfnJNOssED8XB1Ewi/kPeC1mwr0If+QN X-Received: by 2002:a17:90a:a78f:b0:1bc:8042:9330 with SMTP id f15-20020a17090aa78f00b001bc80429330mr21640750pjq.229.1648165983529; Thu, 24 Mar 2022 16:53:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1648165983; cv=none; d=google.com; s=arc-20160816; b=gD6hjYhLNgpI/ohdzNED1EpwRqLNEgBmr++7P1orDyuT2SKfMHrmVeUdFI9HKk2O/d OVp7IvbFnz2iUojvp9g/S2jLfOd8ec4b9AqHhQDQlBhyUKCSB2x+1OxGdXiT32kTuVbZ ZzIOHlnllrI61nosQ8Qt+zCfXDO69XtQRkeSd1rq2qEiKZ66oEwtKge22kLr5vMStvIn QFAjEi9sQs+qa6n85RrqQF3rFUU1gF4DGcv2Rq0zyNL3ABH8dz+517TK5S5xxSJm5sjz iD4FuiLyrJwBOGhO8ZvL5H4pBmlPBNoWZogx+xhX45f4QYzx1axsFIvF6YWFRAV+Pud1 N43w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:in-reply-to:from :references:to:content-language:subject:user-agent:mime-version:date :message-id:dkim-signature; bh=Ny+OtPA6h21ghUzgKKjrwXzddS0ScrUMnjIeLdzE4yo=; b=ezjmZ+l0rVMOlogvHO2jSGRqxpxsIxgMFY2qKJpVsprAX4b8kv7Ipj8Wh+eTW9r9pQ xdY8mGewuTm3fMRdvITKgIe1X+h3F6puAdWnYCy6B4atyJ9796vBxaQXL2jF+vKiKQ8D IjLFjMIfHWs8/W8dCzdDq+pa121x+nCF0mXt7h01lH8BkqekXTg4BsTho8i/F2b/dYjA FDO4kjYmYxkaLMZUs6HMuklYNYwFJtHcwTqlfU0vXBeDXo49vGckJ4dGfa1umAcykdcA 57TZAQ0hNWZqNsp9tzi59z5oSHyOCnD093lpWShLjxthYSl7gtCqbNHJBUtz+tqJ4Sbd UEEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b="My+y2K/x"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 63-20020a630342000000b003816043f0fdsi638119pgd.754.2022.03.24.16.52.50; Thu, 24 Mar 2022 16:53:03 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b="My+y2K/x"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350613AbiCXNwp (ORCPT + 99 others); Thu, 24 Mar 2022 09:52:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47446 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350584AbiCXNwo (ORCPT ); Thu, 24 Mar 2022 09:52:44 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 69136A94C1; Thu, 24 Mar 2022 06:51:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1648129872; x=1679665872; h=message-id:date:mime-version:subject:to:references:from: in-reply-to:content-transfer-encoding; bh=Ny+OtPA6h21ghUzgKKjrwXzddS0ScrUMnjIeLdzE4yo=; b=My+y2K/x7ZpOhDXZuJW+UVGDRqj1kzusmOch18J8+hsk416X6MEQsqyE IyZwqyY8m0B5pfDB8G4uBz6UQmx4KYTXTKNzdjvAj4/avEdc1+TqwyHIY YwJFnNhoabWvDF805NAn+bqua8iRDp/xpzQWFQNh4eK4ulmQn9Zej3sVe 0=; Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 24 Mar 2022 06:51:12 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2022 06:51:12 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 24 Mar 2022 06:51:11 -0700 Received: from [10.110.37.17] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 24 Mar 2022 06:51:10 -0700 Message-ID: <527e9d9e-0dac-3a97-da83-068891a41381@quicinc.com> Date: Thu, 24 Mar 2022 06:51:09 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH v1 2/3] dt-bindings: clock: Add AST2600 video engine reset definition Content-Language: en-US To: Howard Chiu , "robh+dt@kernel.org" , Joel Stanley , "andrew@aj.id.au" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-aspeed@lists.ozlabs.org" , "linux-kernel@vger.kernel.org" References: From: Jae Hyun Yoo In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 3/24/2022 12:27 AM, Howard Chiu wrote: > Reset bit for VE is 6 > > Signed-off-by: Howard Chiu > --- > include/dt-bindings/clock/ast2600-clock.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h > index 62b9520a00fd..a7d0ad9539eb 100644 > --- a/include/dt-bindings/clock/ast2600-clock.h > +++ b/include/dt-bindings/clock/ast2600-clock.h > @@ -110,6 +110,7 @@ > #define ASPEED_RESET_PCIE_DEV_OEN 20 > #define ASPEED_RESET_PCIE_RC_O 19 > #define ASPEED_RESET_PCIE_RC_OEN 18 > +#define ASPEED_RESET_VIDEO 6 You don't need to add 'resets' for video node in DT so it wouldn't be needed. -Jae > #define ASPEED_RESET_PCI_DP 5 > #define ASPEED_RESET_AHB 1 > #define ASPEED_RESET_SDRAM 0