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Sat, 26 Mar 2022 06:57:01 -0700 (PDT) Received: from leoy-ThinkPad-X240s ([104.245.96.34]) by smtp.gmail.com with ESMTPSA id bs7-20020a056402304700b004197e5d2350sm4092657edb.54.2022.03.26.06.56.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 26 Mar 2022 06:57:01 -0700 (PDT) Date: Sat, 26 Mar 2022 21:56:53 +0800 From: Leo Yan To: Arnaldo Carvalho de Melo Cc: Ali Saidi , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-arm-kernel@lists.infradead.org, german.gomez@arm.com, benh@kernel.crashing.org, Nick.Forrington@arm.com, alexander.shishkin@linux.intel.com, andrew.kilroy@arm.com, james.clark@arm.com, john.garry@huawei.com, jolsa@kernel.org, kjain@linux.ibm.com, lihuafei1@huawei.com, mark.rutland@arm.com, mathieu.poirier@linaro.org, mingo@redhat.com, namhyung@kernel.org, peterz@infradead.org, will@kernel.org Subject: Re: [PATCH v4 2/4] perf arm-spe: Use SPE data source for neoverse cores Message-ID: <20220326135653.GE20556@leoy-ThinkPad-X240s> References: <20220324183323.31414-1-alisaidi@amazon.com> <20220324183323.31414-3-alisaidi@amazon.com> <20220326134754.GD20556@leoy-ThinkPad-X240s> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, Mar 26, 2022 at 10:52:01AM -0300, Arnaldo Carvalho de Melo wrote: > Em Sat, Mar 26, 2022 at 09:47:54PM +0800, Leo Yan escreveu: > > Hi Ali, German, > > > > On Thu, Mar 24, 2022 at 06:33:21PM +0000, Ali Saidi wrote: > > > > [...] > > > > > +static void arm_spe__synth_data_source_neoverse(const struct arm_spe_record *record, > > > + union perf_mem_data_src *data_src) > > > { > > > - union perf_mem_data_src data_src = { 0 }; > > > + /* > > > + * Even though four levels of cache hierarchy are possible, no known > > > + * production Neoverse systems currently include more than three levels > > > + * so for the time being we assume three exist. If a production system > > > + * is built with four the this function would have to be changed to > > > + * detect the number of levels for reporting. > > > + */ > > > > > > - if (record->op == ARM_SPE_LD) > > > - data_src.mem_op = PERF_MEM_OP_LOAD; > > > - else > > > - data_src.mem_op = PERF_MEM_OP_STORE; > > > > Firstly, apologize that I didn't give clear idea when Ali sent patch sets > > v2 and v3. > > Ok, removing this as well. > > Thanks for reviewing. Thanks a lot, Arnaldo. Yeah, it's good to give a bit more time to dismiss the concerns in this patch. Sorry again for the inconvenience. Leo