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From:   Ali Saidi <alisaidi@amazon.com>
To:     <leo.yan@linaro.org>
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Subject: Re: [PATCH v4 4/4] perf mem: Support HITM for when mem_lvl_num is any
Date:   Sat, 26 Mar 2022 19:14:54 +0000
Message-ID: <20220326191454.15084-1-alisaidi@amazon.com>
In-Reply-To: <20220326062303.GC20556@leoy-ThinkPad-X240s>
References: <20220326062303.GC20556@leoy-ThinkPad-X240s>
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On Sat, 26 Mar 2022 22:23:03 +0000, Leo Yan wrote:
> On Thu, Mar 24, 2022 at 06:33:23PM +0000, Ali Saidi wrote:
> > For loads that hit in a the LLC snoop filter and are fulfilled from a
> > higher level cache on arm64 Neoverse cores, it's not usually clear what
> > the true level of the cache the data came from (i.e. a transfer from a
> > core could come from it's L1 or L2). Instead of making an assumption of
> > where the line came from, add support for incrementing HITM if the
> > source is CACHE_ANY.A
[snip]
> 
> This might break the memory profiling result for x86, see file
> arch/x86/events/intel/ds.c:
> 
>   97 void __init intel_pmu_pebs_data_source_skl(bool pmem)
>   98 {
>   99         u64 pmem_or_l4 = pmem ? LEVEL(PMEM) : LEVEL(L4);
>   ...
>  105         pebs_data_source[0x0d] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOP, HITM);
>  106 }
> 

Thanks for catching this Leo, I'll add your fix.

Ali