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Message-ID: <53d77f33-27e8-3446-d758-3e545eea2db4@nvidia.com>
Date:   Mon, 28 Mar 2022 13:28:20 +0530
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Subject: Re: [RFC PATCH v2 3/6] ASoC: dt-bindings: Extend clock bindings of
 rt5659
Content-Language: en-US
To:     Krzysztof Kozlowski <krzk@kernel.org>, broonie@kernel.org,
        lgirdwood@gmail.com, robh+dt@kernel.org, krzk+dt@kernel.org,
        perex@perex.cz, tiwai@suse.com, peter.ujfalusi@linux.intel.com,
        pierre-louis.bossart@linux.intel.com
Cc:     oder_chiou@realtek.com, thierry.reding@gmail.com,
        jonathanh@nvidia.com, alsa-devel@alsa-project.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-tegra@vger.kernel.org
References: <1648448050-15237-1-git-send-email-spujar@nvidia.com>
 <1648448050-15237-4-git-send-email-spujar@nvidia.com>
 <da414b44-1bec-5918-84f5-9dfff2009f41@kernel.org>
From:   Sameer Pujar <spujar@nvidia.com>
In-Reply-To: <da414b44-1bec-5918-84f5-9dfff2009f41@kernel.org>
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On 28-03-2022 12:36, Krzysztof Kozlowski wrote:
> External email: Use caution opening links or attachments
>
>
> On 28/03/2022 08:14, Sameer Pujar wrote:
>> The rt5658 or rt5659 CODEC system clock (SYSCLK) can be derived from
>> various clock sources. For example it can be derived either from master
>> clock (MCLK) or by internal PLL. The internal PLL again can take input
>> clock references from bit clocks (BCLKs) and MCLK. To enable a flexible
>> clocking configuration the DT binding is extended here.
>>
>> It makes use of standard clock bindings and sets up the clock relation
>> via DT.
>>
>> Signed-off-by: Sameer Pujar <spujar@nvidia.com>
>> Cc: Oder Chiou <oder_chiou@realtek.com>
>> ---
>>   .../devicetree/bindings/sound/realtek,rt5659.yaml  | 53 ++++++++++++++++++++--
>>   1 file changed, 49 insertions(+), 4 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/sound/realtek,rt5659.yaml b/Documentation/devicetree/bindings/sound/realtek,rt5659.yaml
>> index b0485b8..0c2f3cb 100644
>> --- a/Documentation/devicetree/bindings/sound/realtek,rt5659.yaml
>> +++ b/Documentation/devicetree/bindings/sound/realtek,rt5659.yaml
>> @@ -29,12 +29,28 @@ properties:
>>       maxItems: 1
>>
>>     clocks:
>> -    items:
>> -      - description: Master clock (MCLK) to the CODEC
>> +    description: |
>> +      CODEC can receive multiple clock inputs like Master
>> +      clock (MCLK), I2S bit clocks (BCLK1, BCLK2, BCLK3,
>> +      BCLK4). The CODEC SYSCLK can be generated from MCLK
>> +      or internal PLL. In turn PLL can reference from MCLK
>> +      and BCLKs.
>>
>>     clock-names:
>> -    items:
>> -      - const: mclk
>> +    description: |
>> +      The clock names can be combination of following:
>> +        "mclk"        : Master clock
>> +        "pll_ref"     : Reference to CODEC PLL clock
>> +        "sysclk"      : CODEC SYSCLK
>> +        "^bclk[1-4]$" : Bit clocks to CODEC
> No, that does not look correct. You allow anything as clock input (even
> 20 clocks, different names, any order). That's not how DT schema should
> work and that's not how hardware looks like.

>
> Usually the clock inputs are always there which also you mentioned in
> description - "multiple clock inputs". All these clocks should be
> expected, unless really the wires (physical wires) can be left disconnected.

The CODEC can receive multiple clocks but all the input clocks need not 
be present or connected always. If a specific configuration is needed 
and platform supports such an input, then all these inputs can be added. 
I don't know how to define this detail in the schema. If I make all of 
them expected, then binding check throws errors. If I were to list all 
the possible combinations, the list is going to be big (not sure if this 
would be OK?).