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Message-ID: <e838769b-8b90-79f9-d149-e495667493b5@intel.com>
Date:   Mon, 28 Mar 2022 13:28:39 -0700
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Subject: Re: [PATCH] x86/sgx: Allow RW for TCS pages
Content-Language: en-US
To:     Jarkko Sakkinen <jarkko@kernel.org>, <linux-sgx@vger.kernel.org>
CC:     Dave Hansen <dave.hansen@linux.intel.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
        "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" <x86@kernel.org>,
        "H. Peter Anvin" <hpa@zytor.com>,
        "open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)" 
        <linux-kernel@vger.kernel.org>
References: <20220319163010.101686-1-jarkko@kernel.org>
From:   Reinette Chatre <reinette.chatre@intel.com>
In-Reply-To: <20220319163010.101686-1-jarkko@kernel.org>
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Hi Jarkko,

On 3/19/2022 9:30 AM, Jarkko Sakkinen wrote:
> Not allowing to set RW for added TCS pages leads only to a special case
> to be handled in the user space run-time. Thus, allow permissions to be
> set RW. Originally, it would have probably made more sense to check up
> that the permissions are RW.
> 
> Signed-off-by: Jarkko Sakkinen <jarkko@kernel.org>
> ---
>  arch/x86/kernel/cpu/sgx/ioctl.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/x86/kernel/cpu/sgx/ioctl.c b/arch/x86/kernel/cpu/sgx/ioctl.c
> index 83df20e3e633..f79761ad0400 100644
> --- a/arch/x86/kernel/cpu/sgx/ioctl.c
> +++ b/arch/x86/kernel/cpu/sgx/ioctl.c
> @@ -215,7 +215,7 @@ static int sgx_validate_secinfo(struct sgx_secinfo *secinfo)
>  	 * CPU will silently overwrite the permissions as zero, which means
>  	 * that we need to validate it ourselves.
>  	 */
> -	if (pt == SGX_SECINFO_TCS && perm)
> +	if (pt == SGX_SECINFO_TCS && (perm != 0 || perm != (PROT_READ | PROT_WRITE)))
>  		return -EINVAL;
>  
>  	if (secinfo->flags & SGX_SECINFO_RESERVED_MASK)

The comments above sgx_ioc_enclave_add_pages() seem to indicate that zero 
permissions are required:

"A SECINFO for a TCS is required to always contain zero permissions because
 CPU silently zeros them. Allowing anything else would cause a mismatch in
 the measurement."

Reinette