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Subject: Re: [PATCH 2/5] dt-bindings: phy: Add ARTPEC-8 PCIe phy
Reply-To: wangseok.lee@samsung.com
Sender: =?UTF-8?B?7J207JmV7ISd?= <wangseok.lee@samsung.com>
From:   =?UTF-8?B?7J207JmV7ISd?= <wangseok.lee@samsung.com>
To:     Rob Herring <robh@kernel.org>
CC:     "kernel@axis.com" <kernel@axis.com>,
        "vkoul@kernel.org" <vkoul@kernel.org>,
        "bhelgaas@google.com" <bhelgaas@google.com>,
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        =?UTF-8?B?7KCE66y46riw?= <moonki.jun@samsung.com>,
        "linux-phy@lists.infradead.org" <linux-phy@lists.infradead.org>,
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        "robh+dt@kernel.org" <robh+dt@kernel.org>,
        "jesper.nilsson@axis.com" <jesper.nilsson@axis.com>,
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        "lars.persson@axis.com" <lars.persson@axis.com>
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Message-ID: <20220329052049epcms2p623bd47de38aba8a43689e515bc712ede@epcms2p6>
Date:   Tue, 29 Mar 2022 14:20:49 +0900
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> --------- Original Message ---------
> Sender : Rob Herring=C2=A0<robh=40kernel.org>=0D=0A>=20Date=20:=202022-03=
-28=2021:51=20(GMT+9)=0D=0A>=20Title=20:=20Re:=20=5BPATCH=202/5=5D=20dt-bin=
dings:=20phy:=20Add=20ARTPEC-8=20PCIe=20phy=0D=0A>=20=0D=0A>=20On=C2=A0Mon,=
=C2=A028=C2=A0Mar=C2=A02022=C2=A017:43:19=C2=A0+0900,=C2=A0=EF=BF=BD=EB=8C=
=81=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=C2=A0wrote:=0D=0A>>=C2=A0Add=C2=A0d=
escription=C2=A0to=C2=A0support=C2=A0Axis,=C2=A0ARTPEC-8=C2=A0SoC.=0D=0A>>=
=C2=A0ARTPEC-8=C2=A0is=C2=A0the=C2=A0SoC=C2=A0platform=C2=A0of=C2=A0Axis=C2=
=A0Communications=0D=0A>>=C2=A0and=C2=A0PCIe=C2=A0phy=C2=A0is=C2=A0designed=
=C2=A0based=C2=A0on=C2=A0SAMSUNG=C2=A0PHY.=0D=0A>>=C2=A0=0D=0A>>=C2=A0Signe=
d-off-by:=C2=A0Wangseok=C2=A0Lee=C2=A0<wangseok.lee=40samsung.com>=0D=0A>>=
=C2=A0---=0D=0A>>=C2=A0=C2=A0.../bindings/phy/axis,artpec8-pcie-phy.yaml=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=7C=C2=A067=C2=A0+++++++++++++=
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ons(+)=0D=0A>>=C2=A0=C2=A0create=C2=A0mode=C2=A0100644=C2=A0Documentation/d=
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T_CHECKER_FLAGS=3D-m=C2=A0dt_binding_check'=0D=0A>=20on=C2=A0your=C2=A0patc=
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=0A>=20yamllint=C2=A0warnings/errors:=0D=0A>=20=0D=0A>=20dtschema/dtc=C2=A0=
warnings/errors:=0D=0A>=20Documentation/devicetree/bindings/phy/axis,artpec=
8-pcie-phy.example.dt.yaml:0:0:=C2=A0/example-0/artec8/pcie-phy=4016c80000:=
=C2=A0failed=C2=A0to=C2=A0match=C2=A0any=C2=A0schema=C2=A0with=C2=A0compati=
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rence=C2=A0errors=C2=A0(make=C2=A0refcheckdocs):=0D=0A>=20=0D=0A>=20See=C2=
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heck'=C2=A0and=C2=A0didn't=C2=A0see=C2=A0the=C2=A0above=0D=0A>=20error(s),=
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and=C2=A0dt-schema=C2=A0is=C2=A0up=C2=A0to=0D=0A>=20date:=0D=0A>=20=0D=0A>=
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=C2=A0check=C2=A0and=C2=A0re-submit.=0D=0A=0D=0AHello=20Rob=20Herring=0D=0A=
Thanks=20for=20your=20review.=0D=0A=0D=0AI=20wrote=20the=20wrong=20=22compa=
tible=22=20value.=0D=0Aso=20i=20will=20modify=20this=20part=20and=20summit=
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=0D=0A=22make=20dt_binding_check=20DT_SCHEMA_FILES=3D=0D=0ADocumentation/de=
vicetree/bindings/pci/axis,artpec8-pcie.yaml=22.=0D=0A=0D=0AThanks.