Received: by 2002:a05:6a10:2726:0:0:0:0 with SMTP id ib38csp1489811pxb; Wed, 30 Mar 2022 04:55:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxilAXfbldHBNLh/1N0PNKqEvcqCE0Srtzz6Eqrs1g+dHYMROlGRWVgQWir/0i0wcRD+MMK X-Received: by 2002:a17:906:5418:b0:6df:a07f:764b with SMTP id q24-20020a170906541800b006dfa07f764bmr38045742ejo.27.1648641340118; Wed, 30 Mar 2022 04:55:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1648641340; cv=none; d=google.com; s=arc-20160816; b=tL0A4524PL42KQ96G7xQ2dIHSiZZXNW/HrLdgHz2zzAVuXfTrFwQ+NwkvLRgp88czI QLrWh0tXYwej5M2a6whm3jodCLTiO5b09Ugrdbi0VhnuBqU8E4xmXjO6SAi7V2X4DxZV KnriGRBLjSyxmwRFc8zav+3UCoPuKXEEu/DhLOLrMhzHSwTNB5kdBiMETQTssDQGf2t/ DvVjdlzeovq/PfLIMJWWC17DGRmj5vWB0RxoXxl8bbLbfcI4H4tw+Wu3mdjQJq5hbzGX zSa6KRt6f98/WZroK1UvkYZxdmAG7fEDB68nhMCcezu1suZUqoKz8LFpUs84GJFhGzyt iFkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=cftk6RgTFks6puDFZqlTRAXwEUnZbqFYL0Ls1E12YFM=; b=fkDBKwWc/VCvmRTDJ9gxQD5w/ZNZSMBjGRVecjwiYPvsN5ceC2o69beYcnbY2XxrqC d2ddXWGfcnwEhz5GTMm9/F1SevMK9qtHtJAr5W7W5xgywIUkUo1aJ8x54Z6eQYGOYfPT 59fuIeOspMDcoUfGdjVbUupMIEX0k92V+9V/HwbCEP9E0NmQjLtAmnWP57ZuKx9AJzSO kC1orDz7OyS+1I0No7OCfK1QsPdC1ipTbnU72x+vldVJHnRCKLIkG4WpbL2aKyyg1q57 SM7xLoUk53AF84jGWvEqUoHdGTe6A6H+xcm0aBt/h5oREQNlROuGWkkdaYDVcrwr5/rq PasA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=BJ5HTCW7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id q16-20020a50cc90000000b00418c2b5be49si21738151edi.299.2022.03.30.04.55.13; Wed, 30 Mar 2022 04:55:40 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=BJ5HTCW7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232515AbiC2FmB (ORCPT + 99 others); Tue, 29 Mar 2022 01:42:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55334 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231612AbiC2Fl7 (ORCPT ); Tue, 29 Mar 2022 01:41:59 -0400 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1044131DCB for ; Mon, 28 Mar 2022 22:40:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1648532417; x=1680068417; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ntEI0llQ2lWEuMkMlCRDDWhOOcAZFhuhyEbyMV63nuo=; b=BJ5HTCW7Yhq+TLJc25r044cFFKrAG+ZbITgQmMNcVlN9iJrXnNGmvPqL lBpKavMQjJbRdzGmbTJXaAnTxGOaDLDIZ7kd8cnDIFwE2ehW44voqw89z vUJEpcgrnFNRPOu7+IkDBOFmhRvlDVouwYzJ7LdmsV4QKtPDWp6ZhSkOn Yqx3IeetDOFw4AmoAnmd7LXkCSxbwvamu39HX3L5eZfGPnJSYRfDQca1D 6hoyAOKroXppHCNFxsnB2WYHC3VYRwAyY+ifw7blec836KulUpwreQ4sM HGarmpaCrm5lCjaRSNmS8O9QD1AUktzspMIsSCW1hvOyYD+aF41XpSVGx Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10300"; a="259136963" X-IronPort-AV: E=Sophos;i="5.90,219,1643702400"; d="scan'208";a="259136963" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Mar 2022 22:40:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,219,1643702400"; d="scan'208";a="694603573" Received: from allen-box.sh.intel.com ([10.239.159.48]) by fmsmga001.fm.intel.com with ESMTP; 28 Mar 2022 22:40:13 -0700 From: Lu Baolu To: Joerg Roedel , Jason Gunthorpe , Christoph Hellwig , Kevin Tian , Ashok Raj , Will Deacon , Robin Murphy , Jean-Philippe Brucker Cc: Eric Auger , Liu Yi L , Jacob jun Pan , iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH RFC v2 01/11] iommu: Add pasid_bits field in struct dev_iommu Date: Tue, 29 Mar 2022 13:37:50 +0800 Message-Id: <20220329053800.3049561-2-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220329053800.3049561-1-baolu.lu@linux.intel.com> References: <20220329053800.3049561-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Use this field to save the pasid/ssid bits that a device is able to support with its IOMMU hardware. It is a generic attribute of a device and lifting it into the per-device dev_iommu struct makes it possible to allocate a PASID for device without calls into the IOMMU drivers. Any iommu driver which suports PASID related features should set this field before features are enabled on the devices. Signed-off-by: Lu Baolu --- include/linux/iommu.h | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 2 ++ drivers/iommu/intel/iommu.c | 5 ++++- 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 6ef2df258673..36f43af0af53 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -368,6 +368,7 @@ struct dev_iommu { struct iommu_fwspec *fwspec; struct iommu_device *iommu_dev; void *priv; + unsigned int pasid_bits; }; int iommu_device_register(struct iommu_device *iommu, diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 627a3ed5ee8f..afc63fce6107 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2681,6 +2681,8 @@ static struct iommu_device *arm_smmu_probe_device(struct device *dev) smmu->features & ARM_SMMU_FEAT_STALL_FORCE) master->stall_enabled = true; + dev->iommu->pasid_bits = master->ssid_bits; + return &smmu->iommu; err_free_master: diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 6f7485c44a4b..c1b91bce1530 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -4587,8 +4587,11 @@ static struct iommu_device *intel_iommu_probe_device(struct device *dev) if (pasid_supported(iommu)) { int features = pci_pasid_features(pdev); - if (features >= 0) + if (features >= 0) { info->pasid_supported = features | 1; + dev->iommu->pasid_bits = + fls(pci_max_pasids(pdev)) - 1; + } } if (info->ats_supported && ecap_prs(iommu->ecap) && -- 2.25.1