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[2620:137:e000::1:20]) by mx.google.com with ESMTP id e3-20020a170902ef4300b00153b2d16541si18885425plx.329.2022.03.30.08.56.02; Wed, 30 Mar 2022 08:56:17 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=l9AKUNlJ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232838AbiC2U6i (ORCPT + 99 others); Tue, 29 Mar 2022 16:58:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33842 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232750AbiC2U6g (ORCPT ); Tue, 29 Mar 2022 16:58:36 -0400 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 61662B7C70 for ; Tue, 29 Mar 2022 13:56:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1648587413; x=1680123413; h=date:from:to:cc:subject:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3wtsUueTaQsnYPOimkGDZTAP5s966o4NAmrSveLU4oE=; b=l9AKUNlJl5X1txKkvb0xZDM9CRe6S48qusivz1KFjmcMs4xVWW8YnH4a nOPp1hSH0pScznsC23+NCtJF8Xxt7V4aJ0tkek208rFswo6FsvgjviV64 gTPtSk0ICdhPkRSD4fkD6mWIS6OtGyhJMP+N7LjFRrMx7si4mPL4uyltD zcuh6RzFSSFTSBYaQH5vrmzxK2EtEYxWKAH4wFjpmB3FgfqizAXB74SX6 qsOH/XpSW1OzOdtcX9P+LE5oAFowzLhsxC3igIBJYuZ83CSCwZIz6FmbD JG1ozwOpK4BaVbyEtejeu/C8I58ydAvUiOJAlBbWrxRQbUFPMlRcH9S+Y Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10301"; a="246865461" X-IronPort-AV: E=Sophos;i="5.90,220,1643702400"; d="scan'208";a="246865461" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Mar 2022 13:56:52 -0700 X-IronPort-AV: E=Sophos;i="5.90,220,1643702400"; d="scan'208";a="503048703" Received: from jacob-builder.jf.intel.com (HELO jacob-builder) ([10.7.198.157]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Mar 2022 13:56:52 -0700 Date: Tue, 29 Mar 2022 14:00:15 -0700 From: Jacob Pan To: Lu Baolu Cc: Joerg Roedel , Jason Gunthorpe , Christoph Hellwig , Kevin Tian , Ashok Raj , Will Deacon , Robin Murphy , Jean-Philippe Brucker , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, jacob.jun.pan@intel.com Subject: Re: [PATCH RFC v2 01/11] iommu: Add pasid_bits field in struct dev_iommu Message-ID: <20220329140015.70c073b6@jacob-builder> In-Reply-To: <20220329053800.3049561-2-baolu.lu@linux.intel.com> References: <20220329053800.3049561-1-baolu.lu@linux.intel.com> <20220329053800.3049561-2-baolu.lu@linux.intel.com> Organization: OTC X-Mailer: Claws Mail 3.17.5 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi BaoLu, On Tue, 29 Mar 2022 13:37:50 +0800, Lu Baolu wrote: > Use this field to save the pasid/ssid bits that a device is able to > support with its IOMMU hardware. It is a generic attribute of a device > and lifting it into the per-device dev_iommu struct makes it possible > to allocate a PASID for device without calls into the IOMMU drivers. > Any iommu driver which suports PASID related features should set this > field before features are enabled on the devices. > > Signed-off-by: Lu Baolu > --- > include/linux/iommu.h | 1 + > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 2 ++ > drivers/iommu/intel/iommu.c | 5 ++++- > 3 files changed, 7 insertions(+), 1 deletion(-) > > diff --git a/include/linux/iommu.h b/include/linux/iommu.h > index 6ef2df258673..36f43af0af53 100644 > --- a/include/linux/iommu.h > +++ b/include/linux/iommu.h > @@ -368,6 +368,7 @@ struct dev_iommu { > struct iommu_fwspec *fwspec; > struct iommu_device *iommu_dev; > void *priv; > + unsigned int pasid_bits; pasid_width? PCI spec uses "Max PASID Width" > }; > > int iommu_device_register(struct iommu_device *iommu, > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index > 627a3ed5ee8f..afc63fce6107 100644 --- > a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ > b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2681,6 +2681,8 @@ > static struct iommu_device *arm_smmu_probe_device(struct device *dev) > smmu->features & ARM_SMMU_FEAT_STALL_FORCE) master->stall_enabled = true; > > + dev->iommu->pasid_bits = master->ssid_bits; > + > return &smmu->iommu; > > err_free_master: > diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c > index 6f7485c44a4b..c1b91bce1530 100644 > --- a/drivers/iommu/intel/iommu.c > +++ b/drivers/iommu/intel/iommu.c > @@ -4587,8 +4587,11 @@ static struct iommu_device > *intel_iommu_probe_device(struct device *dev) if (pasid_supported(iommu)) > { int features = pci_pasid_features(pdev); > > - if (features >= 0) > + if (features >= 0) { > info->pasid_supported = features > | 1; > + dev->iommu->pasid_bits = > + > fls(pci_max_pasids(pdev)) - 1; > + } > } > > if (info->ats_supported && ecap_prs(iommu->ecap) > && Thanks, Jacob