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Message-ID: <4399f3cd-6839-73e7-6325-fa1ad6659afa@amd.com>
Date:   Wed, 30 Mar 2022 10:54:27 -0400
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Subject: Re: [PATCH v2] drm/amd/display: don't ignore alpha property on
 pre-multiplied mode
Content-Language: en-US
To:     Rodrigo Siqueira Jordao <rjordrigo@amd.com>,
        Melissa Wen <mwen@igalia.com>,
        Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>,
        Zhan Liu <Zhan.Liu@amd.com>,
        Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>,
        Simon Ser <contact@emersion.fr>
Cc:     amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
        linux-kernel@vger.kernel.org,
        Agustin Gutierrez <agustin.gutierrez@amd.com>,
        Alex Deucher <alexander.deucher@amd.com>,
        markyacoub@google.com, sunpeng.li@amd.com, airlied@linux.ie,
        daniel@ffwll.ch, christian.koenig@amd.com, Xinhui.Pan@amd.com
References: <20220329201835.2393141-1-mwen@igalia.com>
 <f0c7adf6-7417-3773-3780-4a273e9ffb1a@amd.com>
From:   Harry Wentland <harry.wentland@amd.com>
In-Reply-To: <f0c7adf6-7417-3773-3780-4a273e9ffb1a@amd.com>
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On 2022-03-30 08:30, Rodrigo Siqueira Jordao wrote:
> 
> 
> On 2022-03-29 16:18, Melissa Wen wrote:
>> "Pre-multiplied" is the default pixel blend mode for KMS/DRM, as
>> documented in supported_modes of drm_plane_create_blend_mode_property():
>> https://cgit.freedesktop.org/drm/drm-misc/tree/drivers/gpu/drm/drm_blend.c
>>
>> In this mode, both 'pixel alpha' and 'plane alpha' participate in the
>> calculation, as described by the pixel blend mode formula in KMS/DRM
>> documentation:
>>
>> out.rgb = plane_alpha * fg.rgb +
>>            (1 - (plane_alpha * fg.alpha)) * bg.rgb
>>
>> Considering the blend config mechanisms we have in the driver so far,
>> the alpha mode that better fits this blend mode is the
>> _PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN, where the value for global_gain
>> is the plane alpha (global_alpha).
>>
>> With this change, alpha property stops to be ignored. It also addresses
>> Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1734
>>
>> v2:
>>   * keep the 8-bit value for global_alpha_value (Nicholas)
>>   * correct the logical ordering for combined global gain (Nicholas)
>>   * apply to dcn10 too (Nicholas)
>>
>> Signed-off-by: Melissa Wen <mwen@igalia.com>
>> ---
>>   .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 14 +++++++++-----
>>   drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 14 +++++++++-----
>>   2 files changed, 18 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
>> index ad757b59e00e..b1034e6258c8 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
>> @@ -2528,14 +2528,18 @@ void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
>>       struct mpc *mpc = dc->res_pool->mpc;
>>       struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
>>   -    if (per_pixel_alpha)
>> -        blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
>> -    else
>> -        blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
>> -
>>       blnd_cfg.overlap_only = false;
>>       blnd_cfg.global_gain = 0xff;
>>   +    if (per_pixel_alpha && pipe_ctx->plane_state->global_alpha) {
>> +        blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN;
>> +        blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value;
>> +    } else if (per_pixel_alpha) {
>> +        blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
>> +    } else {
>> +        blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
>> +    }
>> +
>>       if (pipe_ctx->plane_state->global_alpha)
>>           blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;
>>       else
>> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
>> index 4290eaf11a04..b627c41713cc 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
>> @@ -2344,14 +2344,18 @@ void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
>>       struct mpc *mpc = dc->res_pool->mpc;
>>       struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
>>   -    if (per_pixel_alpha)
>> -        blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
>> -    else
>> -        blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
>> -
>>       blnd_cfg.overlap_only = false;
>>       blnd_cfg.global_gain = 0xff;
>>   +    if (per_pixel_alpha && pipe_ctx->plane_state->global_alpha) {
>> +        blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN;
>> +        blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value;
>> +    } else if (per_pixel_alpha) {
>> +        blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
>> +    } else {
>> +        blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
>> +    }
>> +
> 
> Hi Melissa,
> 
> Thanks a lot for this patch. I run your patch in our CI, and everything looks good from the IGT test result.
> 
> In this sense:
> Tested-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
> 
> However, I think it is still necessary to have someone else review.
> 
> Harry, Nick, or Zhan, what do you think about this change?
> 

Looks good to me.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>

Harry

> Thanks
> Siqueira
> 
>>       if (pipe_ctx->plane_state->global_alpha)
>>           blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;
>>       else
>