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Date:   Wed, 30 Mar 2022 16:11:45 -0300
From:   Jason Gunthorpe <jgg@nvidia.com>
To:     Bjorn Helgaas <helgaas@kernel.org>
Cc:     Shlomo Pongratz <shlomopongratz@gmail.com>,
        linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
        andrew.maier@eideticom.com, logang@deltatee.com,
        bhelgaas@google.com, Shlomo Pongratz <shlomop@pliops.com>
Subject: Re: [PATCH V4 1/1] Intel Sky Lake-E host root ports check.
Message-ID: <20220330191145.GE2120790@nvidia.com>
References: <20220330153720.GF1716663@nvidia.com>
 <20220330191017.GA1700536@bhelgaas>
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On Wed, Mar 30, 2022 at 02:10:17PM -0500, Bjorn Helgaas wrote:
> On Wed, Mar 30, 2022 at 12:37:20PM -0300, Jason Gunthorpe wrote:
> > On Wed, Mar 30, 2022 at 05:08:23PM +0300, Shlomo Pongratz wrote:
> > > @@ -350,7 +353,10 @@ static struct pci_dev *pci_host_bridge_dev(struct pci_host_bridge *host)
> > >  
> > >  	if (!root)
> > >  		return NULL;
> > > -	if (root->devfn != PCI_DEVFN(0, 0))
> > > +
> > > +	/* Is it a host bridge or a root port? */
> > 
> > This is a better comment:
> > 
> > /* host bridges must have a 0 devfn, but some of the entries in the
> >   whilelist are root ports that can have any devfn */
> 
> Is this something in the spec or is it just common practice?  The PCIe
> spec says very little about "host bridges" and I don't remember
> anything about them having to be devfn 0 or even that they have to be
> materialized as PCI devices.

I think we are relying on common practice here, but I don't know why
this check was added in the first place? Logan?

Jason