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[76.210.143.223]) by smtp.gmail.com with ESMTPSA id 22-20020a17090a019600b001c6457e1760sm339213pjc.21.2022.03.31.15.31.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Mar 2022 15:31:03 -0700 (PDT) Date: Thu, 31 Mar 2022 15:31:03 -0700 (PDT) X-Google-Original-Date: Thu, 31 Mar 2022 13:54:35 PDT (-0700) Subject: Re: [PATCH v2] RISC-V: Enable profiling by default In-Reply-To: <20220324053020.606637-1-apatel@ventanamicro.com> CC: Paul Walmsley , atishp@atishpatra.org, Alistair Francis , anup@brainfault.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, apatel@ventanamicro.com From: Palmer Dabbelt To: apatel@ventanamicro.com Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 23 Mar 2022 22:30:20 PDT (-0700), apatel@ventanamicro.com wrote: > Let us enable profiling by default in RV32 and RV64 defconfigs so > that we can use RISC-V PMU drivers on various RISC-V platforms. > > Signed-off-by: Anup Patel > --- > Changes since v1: > - Enable CONFIG_PROFILING instead of CONFIG_PREF_EVENTS in defconfigs > --- > arch/riscv/configs/defconfig | 1 + > arch/riscv/configs/rv32_defconfig | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig > index f120fcc43d0a..bfebee46784c 100644 > --- a/arch/riscv/configs/defconfig > +++ b/arch/riscv/configs/defconfig > @@ -15,6 +15,7 @@ CONFIG_CHECKPOINT_RESTORE=y > CONFIG_BLK_DEV_INITRD=y > CONFIG_EXPERT=y > # CONFIG_SYSFS_SYSCALL is not set > +CONFIG_PROFILING=y > CONFIG_SOC_MICROCHIP_POLARFIRE=y > CONFIG_SOC_SIFIVE=y > CONFIG_SOC_VIRT=y > diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_defconfig > index 8b56a7f1eb06..2b68b1bd2559 100644 > --- a/arch/riscv/configs/rv32_defconfig > +++ b/arch/riscv/configs/rv32_defconfig > @@ -15,6 +15,7 @@ CONFIG_CHECKPOINT_RESTORE=y > CONFIG_BLK_DEV_INITRD=y > CONFIG_EXPERT=y > # CONFIG_SYSFS_SYSCALL is not set > +CONFIG_PROFILING=y > CONFIG_SOC_SIFIVE=y > CONFIG_SOC_VIRT=y > CONFIG_ARCH_RV32I=y Thanks, this is on for-next.