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Date:   Thu, 31 Mar 2022 14:29:38 +0200
From:   Christoph Hellwig <hch@lst.de>
To:     Heiko Stuebner <heiko@sntech.de>
Cc:     palmer@dabbelt.com, paul.walmsley@sifive.com,
        aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org,
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        allen.baum@esperantotech.com, jscheid@ventanamicro.com,
        rtrauben@gmail.com, samuel@sholland.org, cmuellner@linux.com,
        philipp.tomsich@vrull.eu, Wei Wu <lazyparser@gmail.com>,
        Daniel Lustig <dlustig@nvidia.com>,
        Bill Huffman <huffman@cadence.com>
Subject: Re: [PATCH v8 11/14] riscv: add RISC-V Svpbmt extension support
Message-ID: <20220331122938.GB26108@lst.de>
References: <20220324000710.575331-1-heiko@sntech.de> <20220324000710.575331-12-heiko@sntech.de>
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On Thu, Mar 24, 2022 at 01:07:07AM +0100, Heiko Stuebner wrote:
> +asm(ALTERNATIVE("li %0, 0\t\nnop", "li %0, %1\t\nslli %0,%0,%2", 0,	\
> +		CPUFEATURE_SVPBMT, CONFIG_64BIT)			\
> +		: "=r"(_val) : "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT), "I"(ALT_SVPBMT_SHIFT))

This would be much more readable as;

asm(ALTERNATIVE("li %0, 0\t\nnop", "li %0, %1\t\nslli %0,%0,%2", 0,	\
		CPUFEATURE_SVPBMT, CONFIG_64BIT)			\
		: "=r"(_val)						\
		: "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT),		\
		"I"(ALT_SVPBMT_SHIFT))

Otherwise this looks good to me:

Reviewed-by: Christoph Hellwig <hch@lst.de>