Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Message-ID: <951173dd-0d39-017c-322e-b38f693a8848@linaro.org>
Date:   Fri, 1 Apr 2022 11:32:21 +0200
MIME-Version: 1.0
User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101
 Thunderbird/91.7.0
Subject: Re: [PATCH v12 4/9] dt-bindings: clock: Add bindings for SP7021 clock
 driver
Content-Language: en-US
To:     =?UTF-8?B?cWluamlhblvopoPlgaVd?= <qinjian@cqplus1.com>
Cc:     "robh+dt@kernel.org" <robh+dt@kernel.org>,
        "mturquette@baylibre.com" <mturquette@baylibre.com>,
        "sboyd@kernel.org" <sboyd@kernel.org>,
        "tglx@linutronix.de" <tglx@linutronix.de>,
        "maz@kernel.org" <maz@kernel.org>,
        "p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
        "linux@armlinux.org.uk" <linux@armlinux.org.uk>,
        "arnd@arndb.de" <arnd@arndb.de>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>
References: <cover.1648714851.git.qinjian@cqplus1.com>
 <c535be1e977098993850789faceea1db605df81d.1648714851.git.qinjian@cqplus1.com>
 <84d1e5b6-caa5-cf98-a4b2-2f1ca738b795@linaro.org>
 <eae0d1c49fcd4b41b700e8fd86af1b3e@cqplus1.com>
From:   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
In-Reply-To: <eae0d1c49fcd4b41b700e8fd86af1b3e@cqplus1.com>
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Precedence: bulk

On 01/04/2022 11:19, qinjian[覃健] wrote:
>>> diff --git a/include/dt-bindings/clock/sp-sp7021.h b/include/dt-bindings/clock/sp-sp7021.h
>>> new file mode 100644
>>> index 000000000..45dac6de8
>>> --- /dev/null
>>> +++ b/include/dt-bindings/clock/sp-sp7021.h
>>> @@ -0,0 +1,112 @@
>>> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
>>> +/*
>>> + * Copyright (C) Sunplus Technology Co., Ltd.
>>> + *       All rights reserved.
>>> + */
>>> +#ifndef _DT_BINDINGS_CLOCK_SUNPLUS_SP7021_H
>>> +#define _DT_BINDINGS_CLOCK_SUNPLUS_SP7021_H
>>> +
>>> +#define XTAL			27000000
>>> +
>>> +/* plls */
>>> +#define PLL_A			0
>>> +#define PLL_E			1
>>> +#define PLL_E_2P5		2
>>> +#define PLL_E_25		3
>>> +#define PLL_E_112P5		4
>>> +#define PLL_F			5
>>> +#define PLL_TV			6
>>> +#define PLL_TV_A		7
>>> +#define PLL_SYS			8
>>> +
>>> +/* gates: mo_clken0 ~ mo_clken9 */
>>> +#define CLK_SYSTEM		0x10
>>> +#define CLK_RTC			0x12
>>
>> YAML looks ok, but here comment from Arnd also applies. These should be
>> regular decimal numbers incremented by one.
>>
>> Best regards,
>> Krzysztof
> 
> Yes, same as reset driver, these defines also mapping the hardware.
> But different from reset driver, clk driver also used these defines.
> If I removed this defines, I  must write the proper hardware number twice in dt & driver.
> It's meaningless & hard to check.

Not really... just follow what most (or all) clock drivers are doing -
incremental IDs.


Best regards,
Krzysztof