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Date:   Fri, 01 Apr 2022 15:26:34 -0700 (PDT)
Subject:     Re: [PATCH v3] dt-bindings: Fix phandle-array issues in the idle-states bindings
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CC:     Paul Walmsley <paul.walmsley@sifive.com>, aou@eecs.berkeley.edu,
        anup@brainfault.org, guoren@kernel.org, krzk@kernel.org,
        lorenzo.pieralisi@arm.com, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
From:   Palmer Dabbelt <palmer@rivosinc.com>
To:     Rob Herring <robh@kernel.org>
Message-ID: <mhng-fa8b59bd-f4b0-46c4-90e6-4dd41151afc2@palmer-mbp2014>
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On Fri, 01 Apr 2022 14:39:24 PDT (-0700), Rob Herring wrote:
> On Fri, Apr 1, 2022 at 4:36 PM Palmer Dabbelt <palmer@rivosinc.com> wrote:
>>
>> From: Palmer Dabbelt <palmer@rivosinc.com>
>>
>> As per 39bd2b6a3783 ("dt-bindings: Improve phandle-array schemas"), the
>> phandle-array bindings have been disambiguated.  This fixes the new
>> RISC-V idle-states bindings to comply with the schema.
>>
>> Fixes: 1bd524f7e8d8 ("dt-bindings: Add common bindings for ARM and RISC-V idle states")
>> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
>> ---
>> Changes since v2:
>>
>> * Add the missing schema requirement to riscv/cpus.yaml
>>
>> Changes since v1:
>>
>> * Only fix the RISC-V bindings, to avoid a merge conflict.
>>
>> ---
>>  .../devicetree/bindings/cpu/idle-states.yaml     | 16 ++++++++--------
>>  .../devicetree/bindings/riscv/cpus.yaml          |  2 ++
>>  2 files changed, 10 insertions(+), 8 deletions(-)
>
> Reviewed-by: Rob Herring <robh@kernel.org>
>
> Thanks for fixing quickly.

Well, sorry for breaking it.  I've got the DT checks running locally 
now, we've got a handful of errors in RISC-V land.  I'll clean those up 
and then get something blocking my merges, so stuff like this is less 
likely to happen.

Looks like Linus just merged my Part 2, I'll send along the Part 3 just 
containing this as a fix.