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Mon, 04 Apr 2022 06:50:51 -0700 (PDT) Date: Mon, 4 Apr 2022 06:53:16 -0700 From: Bjorn Andersson To: Johan Hovold Cc: Lorenzo Pieralisi , Stanimir Varbanov , Andy Gross , Rob Herring , Krzysztof Wilczy??ski , Bjorn Helgaas , Dmitry Baryshkov , linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: Re: [PATCH v2] PCI: qcom: Fix pipe clock imbalance Message-ID: References: <20220401133351.10113-1-johan+linaro@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220401133351.10113-1-johan+linaro@kernel.org> X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RDNS_NONE,SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri 01 Apr 06:33 PDT 2022, Johan Hovold wrote: > Commit ed8cc3b1fc84 ("PCI: qcom: Add support for SDM845 PCIe > controller") introduced a clock imbalance by enabling the pipe clock > both in init() and in post_init() but only disabling in post_deinit(). > > Note that the pipe clock was also never disabled in the init() error > paths and that enabling the clock before powering up the PHY looks > questionable. > > Fixes: ed8cc3b1fc84 ("PCI: qcom: Add support for SDM845 PCIe controller") > Cc: stable@vger.kernel.org # 5.6 > Cc: Bjorn Andersson Reviewed-by: Bjorn Andersson > Signed-off-by: Johan Hovold > --- > > Changes in v2 > - Capitalise "Fix" in subject line according to PCI subsystem > convention > > > drivers/pci/controller/dwc/pcie-qcom.c | 6 ------ > 1 file changed, 6 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index b79d98e5e228..20a0e6533a1c 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -1238,12 +1238,6 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) > goto err_disable_clocks; > } > > - ret = clk_prepare_enable(res->pipe_clk); > - if (ret) { > - dev_err(dev, "cannot prepare/enable pipe clock\n"); > - goto err_disable_clocks; > - } > - > /* Wait for reset to complete, required on SM8450 */ > usleep_range(1000, 1500); > > -- > 2.35.1 >