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[2620:137:e000::1:18]) by mx.google.com with ESMTPS id z11-20020a170902708b00b00156a6b13c1esi4173242plk.187.2022.04.04.18.45.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Apr 2022 18:45:22 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:18 as permitted sender) client-ip=2620:137:e000::1:18; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=bk0HoOPN; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id A46A32B3D6B; Mon, 4 Apr 2022 17:44:57 -0700 (PDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354744AbiDBMt3 (ORCPT + 99 others); Sat, 2 Apr 2022 08:49:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45174 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344635AbiDBMt1 (ORCPT ); Sat, 2 Apr 2022 08:49:27 -0400 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D1CD03AA69; Sat, 2 Apr 2022 05:47:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1648903655; x=1680439655; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=VBH8DaxfPRE0Sm3wGsVRsa5H0Vj+YGtrUbWzbb7wQHI=; b=bk0HoOPNIW0pRWX21x6g/RvBFo8Jbi7fND6w/Q3hU3ompAe46hij8WJQ g+LTAJP/jg8HTUbJ8yR/E9FFLf0bfYVDb9C2QodJFoEsbzdpVB/bzIEbX MPk61Dx+wwAkh3TFdvMptTcMYyyUQeYcf+QYaz08X8HB5WhlJnm99RN4Z PWqMzXYXbj/PkdqNXnTSvimY1Ota3F0xQRtiTx64fptCO14LVyzl/olHH y+xUoL8RSTaceiECob/bu6X9Rst72XZiFRwZyem6QqGH53GNQjicZLxPV oNQC2odw7I1SZzUcYMbuElgGkvdEhZDCQdjWQ8FVRZRabcSWAGhL9fIXx w==; X-IronPort-AV: E=McAfee;i="6200,9189,10304"; a="285237935" X-IronPort-AV: E=Sophos;i="5.90,230,1643702400"; d="scan'208";a="285237935" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Apr 2022 05:47:35 -0700 X-IronPort-AV: E=Sophos;i="5.90,230,1643702400"; d="scan'208";a="548131492" Received: from zengguan-mobl1.ccr.corp.intel.com (HELO [10.254.208.38]) ([10.254.208.38]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Apr 2022 05:47:29 -0700 Message-ID: <23fbc97f-05e9-2609-46cc-4320ddc9df12@intel.com> Date: Sat, 2 Apr 2022 20:47:20 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH v7 2/8] KVM: VMX: Extend BUILD_CONTROLS_SHADOW macro to support 64-bit variation Content-Language: en-US To: Sean Christopherson Cc: Paolo Bonzini , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , "kvm@vger.kernel.org" , Dave Hansen , "Luck, Tony" , Kan Liang , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , Kim Phillips , Jarkko Sakkinen , Jethro Beekman , "Huang, Kai" , "x86@kernel.org" , "linux-kernel@vger.kernel.org" , "Hu, Robert" , "Gao, Chao" , Robert Hoo References: <20220304080725.18135-1-guang.zeng@intel.com> <20220304080725.18135-3-guang.zeng@intel.com> From: Zeng Guang In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,NICE_REPLY_A,RDNS_NONE,SPF_HELO_NONE, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 4/1/2022 6:27 AM, Sean Christopherson wrote: > On Fri, Mar 04, 2022, Zeng Guang wrote: >> +#define BUILD_CONTROLS_SHADOW(lname, uname, bits) \ >> +static inline \ >> +void lname##_controls_set(struct vcpu_vmx *vmx, u##bits val) \ >> +{ \ >> + if (vmx->loaded_vmcs->controls_shadow.lname != val) { \ >> + vmcs_write##bits(uname, val); \ >> + vmx->loaded_vmcs->controls_shadow.lname = val; \ >> + } \ >> +} \ >> +static inline u##bits __##lname##_controls_get(struct loaded_vmcs *vmcs)\ >> +{ \ >> + return vmcs->controls_shadow.lname; \ >> +} \ >> +static inline u##bits lname##_controls_get(struct vcpu_vmx *vmx) \ >> +{ \ >> + return __##lname##_controls_get(vmx->loaded_vmcs); \ >> +} \ >> +static inline \ > Drop the newline, there's no need to split this across two lines. Aligning the > backslashes will mean they all poke past the 80 char soft limit, but that's totally > ok. The whole point of the line limit is to improve readability, and a trivial > runover is much less painful than a split function declaration. As a bonus, all > the backslashes are aligned, have leading whitespace, and still land on a tab stop :-) > > #define BUILD_CONTROLS_SHADOW(lname, uname, bits) \ > static inline void lname##_controls_set(struct vcpu_vmx *vmx, u##bits val) \ > { \ > if (vmx->loaded_vmcs->controls_shadow.lname != val) { \ > vmcs_write##bits(uname, val); \ > vmx->loaded_vmcs->controls_shadow.lname = val; \ > } \ > } \ > static inline u##bits __##lname##_controls_get(struct loaded_vmcs *vmcs) \ > { \ > return vmcs->controls_shadow.lname; \ > } \ > static inline u##bits lname##_controls_get(struct vcpu_vmx *vmx) \ > { \ > return __##lname##_controls_get(vmx->loaded_vmcs); \ > } \ > static inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u##bits val) \ > { \ > lname##_controls_set(vmx, lname##_controls_get(vmx) | val); \ > } \ > static inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u##bits val) \ > { \ > lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val); \ > } > > With that fixed, > > Reviewed-by: Sean Christopherson OK. I'll revise it.