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(unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 6862122249; Tue, 5 Apr 2022 14:09:57 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1649160597; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=p7la0KOeEOAysVBijkaFTCkW3yqx5mQnMD3fZ7uHfuI=; b=Xm1ftZagfg7DLK0rvHGkDSHaDN+b4oWWx/v6NA93MNQVtCI99qnP+321I8bYQVe9h5qJG2 Lv8i+AxwwSew01k/OSou8MVw41i+jDofX1P/ZjGF7EaWNTBVB8uyl9KswtPYS1E6w4SAJY 66EvyEMJX/5aVVGmyqYX9jj13NDquV8= From: Michael Walle To: "David S . Miller" , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Andrew Lunn , Heiner Kallweit , Russell King , Alexandre Belloni Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Walle , Krzysztof Kozlowski Subject: [PATCH net-next v3 2/3] dt-bindings: net: mscc-miim: add clock and clock-frequency Date: Tue, 5 Apr 2022 14:09:50 +0200 Message-Id: <20220405120951.4044875-3-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220405120951.4044875-1-michael@walle.cc> References: <20220405120951.4044875-1-michael@walle.cc> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RDNS_NONE,SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the (optional) clock input of the MDIO controller and indicate that the common clock-frequency property is supported. The driver can use it to set the desired MDIO bus frequency. Signed-off-by: Michael Walle Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/net/mscc,miim.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/net/mscc,miim.yaml b/Documentation/devicetree/bindings/net/mscc,miim.yaml index cdc39aa20683..2c451cfa4e0b 100644 --- a/Documentation/devicetree/bindings/net/mscc,miim.yaml +++ b/Documentation/devicetree/bindings/net/mscc,miim.yaml @@ -33,6 +33,11 @@ properties: interrupts: maxItems: 1 + clocks: + maxItems: 1 + + clock-frequency: true + required: - compatible - reg -- 2.30.2