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Message-ID: <94758036-b697-6e7d-2a44-bb0c698b5e5a@intel.com>
Date:   Tue, 5 Apr 2022 09:00:28 -0700
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Subject: Re: [PATCH v3 1/5] fpga: zynq: Fix incorrect variable type
Content-Language: en-US
To:     Xu Yilun <yilun.xu@intel.com>,
        Nava kishore Manne <nava.manne@xilinx.com>
CC:     <mdf@kernel.org>, <hao.wu@intel.com>, <trix@redhat.com>,
        <michal.simek@xilinx.com>, <linux-fpga@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>, <git@xilinx.com>
References: <20220403051641.3867610-1-nava.manne@xilinx.com>
 <20220403051641.3867610-2-nava.manne@xilinx.com>
 <20220405043804.GA248628@yilunxu-OptiPlex-7050>
From:   Russ Weight <russell.h.weight@intel.com>
In-Reply-To: <20220405043804.GA248628@yilunxu-OptiPlex-7050>
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On 4/4/22 21:38, Xu Yilun wrote:
> On Sun, Apr 03, 2022 at 10:46:37AM +0530, Nava kishore Manne wrote:
>> zynq_fpga_has_sync () API is expecting "u8 *" but the
>> formal parameter that was passed is of type "const char *".
>> fixes this issue by changing the buf type to "const char *"
>   Fix
>
>> This patch will also update zynq_fpga_has_sync () API description
>> to align with API functionality.
>>
>> Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
>> ---
>> Changes for v2:
>>                 -None.
>> Changes for v3:
>>                - Changed arg buf type to "const char *" as suggested by Tom.
>>
>>  drivers/fpga/zynq-fpga.c | 8 ++++----
>>  1 file changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c
>> index 426aa34c6a0d..ada07eea64bc 100644
>> --- a/drivers/fpga/zynq-fpga.c
>> +++ b/drivers/fpga/zynq-fpga.c
>> @@ -235,11 +235,11 @@ static irqreturn_t zynq_fpga_isr(int irq, void *data)
>>  	return IRQ_HANDLED;
>>  }
>>  
>> -/* Sanity check the proposed bitstream. It must start with the sync word in
>> - * the correct byte order, and be dword aligned. The input is a Xilinx .bin
>> - * file with every 32 bit quantity swapped.
>> +/* Sanity check the proposed bitstream. The sync word must be found in the
>> + * correct byte order and it should be dword aligned. The input is a
>> + * Xilinx.bin file with every 32 bit quantity swapped.
> I didn't found these changes in v2, or in change logs. Please record it.
>
> Sorry, as a foreign English user, I didn't find the necessity of the change.
> The previous words are as clear as the current. Anyone could help?

I think the change adds a little clarity to the second sentence.

- Russ
>
> And they are not for variable type fix. Please make a separate patch if
> really needed.
>
> Thanks,
> Yilun
>
>>   */
>> -static bool zynq_fpga_has_sync(const u8 *buf, size_t count)
>> +static bool zynq_fpga_has_sync(const char *buf, size_t count)
>>  {
>>  	for (; count >= 4; buf += 4, count -= 4)
>>  		if (buf[0] == 0x66 && buf[1] == 0x55 && buf[2] == 0x99 &&
>> -- 
>> 2.25.1