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Date:   Tue, 05 Apr 2022 20:57:08 -0000
From:   tip-bot2 for Ricardo =?utf-8?q?Ca=C3=B1uelo?= 
        <tip-bot2@linutronix.de>
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To:     linux-tip-commits@vger.kernel.org
Subject: [tip: x86/cpu] x86/speculation/srbds: Do not try to turn mitigation
 off when not supported
Cc:     Pawan Gupta <pawan.kumar.gupta@linux.intel.com>,
        ricardo.canuelo@collabora.com, Borislav Petkov <bp@suse.de>,
        x86@kernel.org, linux-kernel@vger.kernel.org
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The following commit has been merged into the x86/cpu branch of tip:

Commit-ID:     0205f8a738ab9e62d849e88e543cfa6ce4c13163
Gitweb:        https://git.kernel.org/tip/0205f8a738ab9e62d849e88e543cfa6ce4c=
13163
Author:        Ricardo Ca=C3=B1uelo <ricardo.canuelo@collabora.com>
AuthorDate:    Fri, 01 Apr 2022 09:45:17 +02:00
Committer:     Borislav Petkov <bp@suse.de>
CommitterDate: Tue, 05 Apr 2022 21:55:57 +02:00

x86/speculation/srbds: Do not try to turn mitigation off when not supported

When SRBDS is mitigated by TSX OFF, update_srbds_msr() will still read
and write to MSR_IA32_MCU_OPT_CTRL even when that MSR is not supported
due to not having loaded the appropriate microcode.

Check for X86_FEATURE_SRBDS_CTRL which is set only when the respective
microcode which adds MSR_IA32_MCU_OPT_CTRL is loaded.

Based on a patch by Thadeu Lima de Souza Cascardo <cascardo@canonical.com>.

  [ bp: Massage commit message. ]

Suggested-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Signed-off-by: Ricardo Ca=C3=B1uelo <ricardo.canuelo@collabora.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lore.kernel.org/r/20220401074517.1848264-1-ricardo.canuelo@coll=
abora.com
---
 arch/x86/kernel/cpu/bugs.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index 6296e1e..d879a6c 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -446,6 +446,13 @@ void update_srbds_msr(void)
 	if (srbds_mitigation =3D=3D SRBDS_MITIGATION_UCODE_NEEDED)
 		return;
=20
+	/*
+	 * A MDS_NO CPU for which SRBDS mitigation is not needed due to TSX
+	 * being disabled and it hasn't received the SRBDS MSR microcode.
+	 */
+	if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL))
+		return;
+
 	rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
=20
 	switch (srbds_mitigation) {