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Date:   Tue, 5 Apr 2022 10:14:20 -0700
From:   Matthias Kaehlcke <mka@chromium.org>
To:     Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Cc:     agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org,
        linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, quic_rohitkr@quicinc.com,
        srinivas.kandagatla@linaro.org, dianders@chromium.org,
        swboyd@chromium.org, judyhsiao@chromium.org,
        Venkata Prasad Potturu <quic_potturu@quicinc.com>
Subject: Re: [PATCH v6 2/2] arm64: dts: qcom: sc7280: add lpass lpi pin
 controller node
Message-ID: <Ykx47AlGYa8s5FTa@google.com>
References: <1649157167-29106-1-git-send-email-quic_srivasam@quicinc.com>
 <1649157167-29106-3-git-send-email-quic_srivasam@quicinc.com>
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On Tue, Apr 05, 2022 at 04:42:47PM +0530, Srinivasa Rao Mandadapu wrote:
> Add LPASS LPI pinctrl node required for Audio functionality on sc7280
> based platforms.
> 
> Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
> Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
> Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/sc7280-idp.dtsi |  98 ++++++++++++++++++++++++++++
>  arch/arm64/boot/dts/qcom/sc7280.dtsi     | 107 +++++++++++++++++++++++++++++++
>  2 files changed, 205 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
> index 2afbbe3..f912a89 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
> @@ -238,6 +238,104 @@
>  	modem-init;
>  };
>  
> +&lpass_tlmm {
> +	dmic01_active: dmic01-active {
> +		clk {
> +			drive-strength = <8>;
> +		};
> +
> +		data {
> +			drive-strength = <8>;

The DMIC data pins are input pins, right? Why does an input pin need a drive
strength? Same for other input pins.

> +		};
> +	};

There's no need to reference 'lpass_tlmm' nor to repeat $label: $node.
Instead just use phandles:

&dmic01_active {
	clk {
		drive-strength = <8>;
	};

	data {
		drive-strength = <8>;
	};
};

Rather than replicating the node hierarchy you could also just give each pin a
label, and then:

&dmic01_clk_active {
	drive-strength = <8>;
};

&dmic01_data_active {
	drive-strength = <8>;
};

I don't have a strong preference, but wonder if the grouping adds any value.

> +
> +	dmic01_sleep: dmic01-sleep {
> +		clk {
> +			drive-strength = <2>;
> +			bias-disable;
> +		};
> +
> +		data {
> +			drive-strength = <2>;
> +			pull-down;
> +		};
> +	};
> +
> +	dmic23_active: dmic02-active {
> +		clk {
> +			drive-strength = <8>;
> +		};
> +
> +		data {
> +			drive-strength = <8>;
> +		};
> +	};
> +
> +	dmic23_sleep: dmic02-sleep {
> +		clk {
> +			drive-strength = <2>;
> +			bias-disable;
> +		};
> +
> +		data {
> +			drive-strength = <2>;
> +			pull-down;
> +		};
> +	};
> +
> +	rx_swr_active: rx-swr-active {
> +		clk {
> +			drive-strength = <2>;
> +			slew-rate = <1>;
> +			bias-disable;
> +		};
> +
> +		data {
> +			drive-strength = <2>;
> +			slew-rate = <1>;
> +			bias-bus-hold;
> +		};
> +	};
> +
> +	rx_swr_sleep: rx-swr-sleep {
> +		clk {
> +			drive-strength = <2>;
> +			bias-pull-down;
> +		};
> +
> +		data {
> +			drive-strength = <2>;
> +			bias-pull-down;
> +		};
> +	};
> +
> +	tx_swr_active: tx-swr-active {
> +		clk {
> +			drive-strength = <2>;
> +			slew-rate = <1>;
> +			bias-disable;
> +		};
> +
> +		data {
> +			drive-strength = <2>;
> +			slew-rate = <1>;
> +			bias-bus-hold;
> +		};
> +	};
> +
> +	tx_swr_sleep: tx-swr-sleep {
> +		clk {
> +			drive-strength = <2>;
> +			bias-pull-down;
> +		};
> +
> +		data {
> +			drive-strength = <2>;
> +			bias-bus-hold;
> +		};
> +	};
> +};
> +
>  &pcie1 {
>  	status = "okay";
>  	perst-gpio = <&tlmm 2 GPIO_ACTIVE_LOW>;
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 8d8cec5..db74fc3 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -1987,6 +1987,113 @@
>  			qcom,bcm-voters = <&apps_bcm_voter>;
>  		};
>  
> +		lpass_tlmm: pinctrl@33c0000 {
> +			compatible = "qcom,sc7280-lpass-lpi-pinctrl";
> +			reg = <0 0x33c0000 0x0 0x20000>,
> +				<0 0x3550000 0x0 0x10000>;

Pad addresses to 8 digits.

> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&lpass_tlmm 0 0 15>;
> +
> +			#clock-cells = <1>;
> +
> +			dmic01_active: dmic01-active {
> +				clk {
> +					pins = "gpio6";
> +					function = "dmic1_clk";
> +				};
> +
> +				data {
> +					pins = "gpio7";
> +					function = "dmic1_data";
> +				};
> +			};
> +
> +			dmic01_sleep: dmic01-sleep {
> +				clk {
> +					pins = "gpio6";
> +					function = "dmic1_clk";
> +				};
> +
> +				data {
> +					pins = "gpio7";
> +					function = "dmic1_data";
> +				};
> +			};
> +
> +			dmic23_active: dmic02-active {

is it intentional that the node name is 'dmic02*', but the label 'dmic23*'?

> +				clk {
> +					pins = "gpio8";
> +					function = "dmic2_clk";
> +				};
> +
> +				data {
> +					pins = "gpio9";
> +					function = "dmic2_data";
> +				};
> +			};
> +
> +			dmic23_sleep: dmic02-sleep {

ditto

> +				clk {
> +					pins = "gpio8";
> +					function = "dmic2_clk";
> +				};
> +
> +				data {
> +					pins = "gpio9";
> +					function = "dmic2_data";
> +				};
> +			};
> +
> +			rx_swr_active: rx-swr-active {
> +				clk {
> +					pins = "gpio3";
> +					function = "swr_rx_clk";
> +				};
> +
> +				data {
> +					pins = "gpio4", "gpio5";
> +					function = "swr_rx_data";
> +				};
> +			};
> +
> +			rx_swr_sleep: rx-swr-sleep {
> +				clk {
> +					pins = "gpio3";
> +					function = "swr_rx_clk";
> +				};
> +
> +				data {
> +					pins = "gpio4", "gpio5";
> +					function = "swr_rx_data";
> +				};
> +			};
> +
> +			tx_swr_active: tx-swr-active {
> +				clk {
> +					pins = "gpio0";
> +					function = "swr_tx_clk";
> +				};
> +
> +				data {
> +					pins = "gpio1", "gpio2", "gpio14";
> +					function = "swr_tx_data";
> +				};
> +			};
> +
> +			tx_swr_sleep: tx-swr-sleep {
> +				clk {
> +					pins = "gpio0";
> +					function = "swr_tx_clk";
> +				};
> +
> +				data {
> +					pins = "gpio1", "gpio2", "gpio14";
> +					function = "swr_tx_data";
> +				};
> +			};
> +		};
> +
>  		gpu: gpu@3d00000 {
>  			compatible = "qcom,adreno-635.0", "qcom,adreno";
>  			reg = <0 0x03d00000 0 0x40000>,