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Peter Anvin" , Russ Anderson , linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org Subject: Re: [PATCH v4 0/3] x86/platform/uv: UV Kernel support for UV5 In-Reply-To: <20220406195149.228164-1-steve.wahl@hpe.com> References: <20220406195149.228164-1-steve.wahl@hpe.com> Date: Thu, 07 Apr 2022 00:53:08 +0200 Message-ID: <87k0c1zuwb.ffs@tglx> MIME-Version: 1.0 Content-Type: text/plain X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Apr 06 2022 at 14:51, Steve Wahl wrote: > v2: Delete patch to remove SCRATCH 5 NMI support check for > UV2 and UV3k systems with old NMI support function. > > v3: Fix check BIOS NMI support mistake in Patch 1. > > v4: Clarify commit messages and comments in all 3 patches. > We hope this addresses the issues raised by Thomas Gleixner in > https://lore.kernel.org/r/87zgl02w6v.ffs@tglx > > Update NMI Handler for UV5 > Update NMI handler for UV5 hardware. A platform register > changed, and UV5 only uses one of the two NMI methods used on > previous hardware. > > Update TSC sync state for UV5 > > The UV5 platform synchronizes the TSCs among all chassis, and > will not proceed to OS boot without achieving synchronization. > Previous UV platforms provided a register indicating > successful synchronization. This is no longer available on > UV5. On this platform TSC_ADJUST should not be reset by the > kernel. > > Log gap hole end size > Show value of gap end in the kernel log which equates to > number of physical address bits used by system. > > Mike Travis (3): > x86/platform/uv: Update NMI Handler for UV5 > x86/platform/uv: Update TSC sync state for UV5 > x86/platform/uv: Log gap hole end size Acked-by: Thomas Gleixner