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From:   Alex Deucher <alexdeucher@gmail.com>
Date:   Thu, 7 Apr 2022 13:46:05 -0400
Message-ID: <CADnq5_NXzEzo=6adPQzEBrAGtWfegyvi=yGHVVOsb+3r9OiNaQ@mail.gmail.com>
Subject: Re: [PATCH] drm/amdgpu: Fix code with incorrect enum type
To:     =?UTF-8?Q?Christian_K=C3=B6nig?= <ckoenig.leichtzumerken@gmail.com>
Cc:     Grigory Vasilyev <h0tc0d3@gmail.com>,
        Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>,
        Melissa Wen <mwen@igalia.com>, Daniel Vetter <daniel@ffwll.ch>,
        Guchun Chen <guchun.chen@amd.com>,
        David Airlie <airlied@linux.ie>,
        "Pan, Xinhui" <Xinhui.Pan@amd.com>,
        LKML <linux-kernel@vger.kernel.org>,
        amd-gfx list <amd-gfx@lists.freedesktop.org>,
        Maling list - DRI developers 
        <dri-devel@lists.freedesktop.org>,
        Joseph Greathouse <Joseph.Greathouse@amd.com>,
        Alex Deucher <alexander.deucher@amd.com>,
        Evan Quan <evan.quan@amd.com>,
        =?UTF-8?Q?Christian_K=C3=B6nig?= <christian.koenig@amd.com>
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On Thu, Apr 7, 2022 at 2:21 AM Christian K=C3=B6nig
<ckoenig.leichtzumerken@gmail.com> wrote:
>
> Am 06.04.22 um 18:50 schrieb Grigory Vasilyev:
> > Instead of the 'amdgpu_ring_priority_level' type,
> > the 'amdgpu_gfx_pipe_priority' type was used,
> > which is an error when setting ring priority.
> > This is a minor error, but may cause problems in the future.
> >
> > Instead of AMDGPU_RING_PRIO_2 =3D 2, we can use AMDGPU_RING_PRIO_MAX =
=3D 3,
> > but AMDGPU_RING_PRIO_2 =3D 2 is used for compatibility with
> > AMDGPU_GFX_PIPE_PRIO_HIGH =3D 2, and not change the behavior of the
> > code.
> >
> > Signed-off-by: Grigory Vasilyev <h0tc0d3@gmail.com>
>
> Good catch, Acked-by: Christian K=C3=B6nig <christian.koenig@amd.com>
>
> > ---
> >   drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/am=
d/amdgpu/gfx_v8_0.c
> > index 5554084ec1f1..9bc26395f833 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> > @@ -1929,7 +1929,7 @@ static int gfx_v8_0_compute_ring_init(struct amdg=
pu_device *adev, int ring_id,
> >               + ring->pipe;
> >
> >       hw_prio =3D amdgpu_gfx_is_high_priority_compute_queue(adev, ring)=
 ?
> > -                     AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_RING_PRIO_DEFA=
ULT;
> > +                     AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT;

gfx_v8_0.c, gfx_v9_0.c, gfx_v10_0.c all do this.  Care to fix them all up?

Alex

> >       /* type-2 packets are deprecated on MEC, use type-3 instead */
> >       r =3D amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_=
type,
> >                            hw_prio, NULL);
>