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Message-ID: <bb7635cf-461e-7abd-6092-4be67099c846@amd.com>
Date:   Thu, 7 Apr 2022 10:18:14 -0400
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Subject: Re: [PATCH] drm/amd/display: Fix indenting mistakes in
 dcn10_hw_sequencer.c
Content-Language: en-US
To:     Haowen Bai <baihaowen@meizu.com>, Leo Li <sunpeng.li@amd.com>,
        Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>,
        Alex Deucher <alexander.deucher@amd.com>,
        =?UTF-8?Q?Christian_K=c3=b6nig?= <christian.koenig@amd.com>,
        "Pan, Xinhui" <Xinhui.Pan@amd.com>,
        David Airlie <airlied@linux.ie>,
        Daniel Vetter <daniel@ffwll.ch>
Cc:     dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org,
        linux-kernel@vger.kernel.org
References: <1649311250-17077-1-git-send-email-baihaowen@meizu.com>
From:   Harry Wentland <harry.wentland@amd.com>
In-Reply-To: <1649311250-17077-1-git-send-email-baihaowen@meizu.com>
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On 2022-04-07 02:00, Haowen Bai wrote:
> Smatch reports the following:
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:2174
> dcn10_enable_vblanks_synchronization() warn: if statement not indented
> 
> Signed-off-by: Haowen Bai <baihaowen@meizu.com>

Reviewed-by: Harry Wentland <harry.wentland@amd.com>

Harry

> ---
>  drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 14 +++++++-------
>  1 file changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> index ee22f4422d26..3c338b85040c 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> @@ -2172,13 +2172,13 @@ void dcn10_enable_vblanks_synchronization(
>  	if (master >= 0) {
>  		for (i = 0; i < group_size; i++) {
>  			if (i != master && !grouped_pipes[i]->stream->has_non_synchronizable_pclk)
> -			grouped_pipes[i]->stream_res.tg->funcs->align_vblanks(
> -				grouped_pipes[master]->stream_res.tg,
> -				grouped_pipes[i]->stream_res.tg,
> -				grouped_pipes[master]->stream->timing.pix_clk_100hz,
> -				grouped_pipes[i]->stream->timing.pix_clk_100hz,
> -				get_clock_divider(grouped_pipes[master], false),
> -				get_clock_divider(grouped_pipes[i], false));
> +				grouped_pipes[i]->stream_res.tg->funcs->align_vblanks(
> +					grouped_pipes[master]->stream_res.tg,
> +					grouped_pipes[i]->stream_res.tg,
> +					grouped_pipes[master]->stream->timing.pix_clk_100hz,
> +					grouped_pipes[i]->stream->timing.pix_clk_100hz,
> +					get_clock_divider(grouped_pipes[master], false),
> +					get_clock_divider(grouped_pipes[i], false));
>  				grouped_pipes[i]->stream->vblank_synchronized = true;
>  		}
>  		grouped_pipes[master]->stream->vblank_synchronized = true;