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Date:   Fri, 8 Apr 2022 11:46:59 -0700
From:   Isaku Yamahata <isaku.yamahata@gmail.com>
To:     Paolo Bonzini <pbonzini@redhat.com>
Cc:     isaku.yamahata@intel.com, kvm@vger.kernel.org,
        linux-kernel@vger.kernel.org, isaku.yamahata@gmail.com,
        Jim Mattson <jmattson@google.com>, erdemaktas@google.com,
        Connor Kuehl <ckuehl@redhat.com>,
        Sean Christopherson <seanjc@google.com>
Subject: Re: [RFC PATCH v5 042/104] KVM: x86/mmu: Track shadow MMIO
 value/mask on a per-VM basis
Message-ID: <20220408184659.GC857847@ls.amr.corp.intel.com>
References: <cover.1646422845.git.isaku.yamahata@intel.com>
 <b494b94bf2d6a5d841cb76e63e255d4cff906d83.1646422845.git.isaku.yamahata@intel.com>
 <84d56339-4a8a-6ddb-17cb-12074588ba9c@redhat.com>
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On Tue, Apr 05, 2022 at 05:25:34PM +0200,
Paolo Bonzini <pbonzini@redhat.com> wrote:

> On 3/4/22 20:48, isaku.yamahata@intel.com wrote:
> > +	if (enable_ept) {
> > +		const u64 init_value = enable_tdx ? VMX_EPT_SUPPRESS_VE_BIT : 0ull;
> >   		kvm_mmu_set_ept_masks(enable_ept_ad_bits,
> > -				      cpu_has_vmx_ept_execute_only());
> > +				      cpu_has_vmx_ept_execute_only(), init_value);
> > +		kvm_mmu_set_spte_init_value(init_value);
> > +	}
> 
> I think kvm-intel.ko should use VMX_EPT_SUPPRESS_VE_BIT unconditionally as
> the init value.  The bit is ignored anyway if the "EPT-violation #VE"
> execution control is 0.  Otherwise looks good, but I have a couple more
> crazy ideas:
> 
> 1) there could even be a test mode where KVM enables the execution control,
> traps #VE in the exception bitmap, and shouts loudly if it gets a #VE.  That
> might avoid hard-to-find bugs due to forgetting about
> VMX_EPT_SUPPRESS_VE_BIT.
> 
> 2) or even, perhaps the init_value for the TDP MMU could set bit 63
> _unconditionally_, because KVM always sets the NX bit on AMD hardware. That
> would remove the whole infrastructure to keep shadow_init_value, because it
> would be constant 0 in mmu.c and constant BIT(63) in tdp_mmu.c.
> 
> Sean, what do you think?

Then, I'll start with 1) because it's a bit hard for me to test 2) with real AMD
hardware.  If someone is willing to test 2), I'm quite fine to implement 2)
on top of 1).  2) isn't exclusive with 1).
-- 
Isaku Yamahata <isaku.yamahata@gmail.com>