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To i.MX8M, there is CCM(clock control Module) to generate > clock root clock, anatop(analog PLL module) to generate PLL, and CCGR > (clock gating) to gate clocks to peripherals. As below: > anatop->ccm->ccgr->peripheral > > Linux handles the clock management and the auxiliary core is under > control of Linux. Although there is per hardware domain control for CCGR > and CCM, auxiliary core normally only use CCGR hardware domain control > to avoid linux gate off the clk to peripherals and leave CCM ana anatop > to Linux. > > Per NXP hardware design, because CCGR already support gate to > peripherals, and clk root gate power leakage is negligible. So > when in AMP case, we could not register the clk root gate. > > Signed-off-by: Peng Fan Applied both, thanks. > --- > > V2: > Switch to use module parameter, tested on i.MX8MP-EVK > > drivers/clk/imx/clk-imx8mm.c | 2 ++ > drivers/clk/imx/clk-imx8mn.c | 2 ++ > drivers/clk/imx/clk-imx8mp.c | 2 ++ > drivers/clk/imx/clk-imx8mq.c | 2 ++ > drivers/clk/imx/clk.c | 3 +++ > drivers/clk/imx/clk.h | 1 + > 6 files changed, 12 insertions(+) > > diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c > index e8cbe181ec06..a452fd1bb891 100644 > --- a/drivers/clk/imx/clk-imx8mm.c > +++ b/drivers/clk/imx/clk-imx8mm.c > @@ -639,6 +639,8 @@ static struct platform_driver imx8mm_clk_driver = { > }, > }; > module_platform_driver(imx8mm_clk_driver); > +module_param(mcore_booted, bool, S_IRUGO); > +MODULE_PARM_DESC(mcore_booted, "See Cortex-M core is booted or not"); > > MODULE_AUTHOR("Bai Ping "); > MODULE_DESCRIPTION("NXP i.MX8MM clock driver"); > diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c > index 92fcbab4f5be..dc69b7464b3d 100644 > --- a/drivers/clk/imx/clk-imx8mn.c > +++ b/drivers/clk/imx/clk-imx8mn.c > @@ -594,6 +594,8 @@ static struct platform_driver imx8mn_clk_driver = { > }, > }; > module_platform_driver(imx8mn_clk_driver); > +module_param(mcore_booted, bool, S_IRUGO); > +MODULE_PARM_DESC(mcore_booted, "See Cortex-M core is booted or not"); > > MODULE_AUTHOR("Anson Huang "); > MODULE_DESCRIPTION("NXP i.MX8MN clock driver"); > diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c > index 18f5b7c3ca9d..250e45d9f844 100644 > --- a/drivers/clk/imx/clk-imx8mp.c > +++ b/drivers/clk/imx/clk-imx8mp.c > @@ -721,6 +721,8 @@ static struct platform_driver imx8mp_clk_driver = { > }, > }; > module_platform_driver(imx8mp_clk_driver); > +module_param(mcore_booted, bool, S_IRUGO); > +MODULE_PARM_DESC(mcore_booted, "See Cortex-M core is booted or not"); > > MODULE_AUTHOR("Anson Huang "); > MODULE_DESCRIPTION("NXP i.MX8MP clock driver"); > diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c > index 83cc2b1c3294..33897b56130d 100644 > --- a/drivers/clk/imx/clk-imx8mq.c > +++ b/drivers/clk/imx/clk-imx8mq.c > @@ -632,6 +632,8 @@ static struct platform_driver imx8mq_clk_driver = { > }, > }; > module_platform_driver(imx8mq_clk_driver); > +module_param(mcore_booted, bool, S_IRUGO); > +MODULE_PARM_DESC(mcore_booted, "See Cortex-M core is booted or not"); > > MODULE_AUTHOR("Abel Vesa "); > MODULE_DESCRIPTION("NXP i.MX8MQ clock driver"); > diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c > index 7cc669934253..4bd6ad060eea 100644 > --- a/drivers/clk/imx/clk.c > +++ b/drivers/clk/imx/clk.c > @@ -17,6 +17,9 @@ > DEFINE_SPINLOCK(imx_ccm_lock); > EXPORT_SYMBOL_GPL(imx_ccm_lock); > > +bool mcore_booted; > +EXPORT_SYMBOL_GPL(mcore_booted); > + > void imx_unregister_clocks(struct clk *clks[], unsigned int count) > { > unsigned int i; > diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h > index a7cbbcd1a3f4..5061a06468df 100644 > --- a/drivers/clk/imx/clk.h > +++ b/drivers/clk/imx/clk.h > @@ -7,6 +7,7 @@ > #include > > extern spinlock_t imx_ccm_lock; > +extern bool mcore_booted; > > void imx_check_clocks(struct clk *clks[], unsigned int count); > void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count); > -- > 2.25.1 >