Received: by 2002:a05:6a10:6d10:0:0:0:0 with SMTP id gq16csp815998pxb; Tue, 12 Apr 2022 14:14:12 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwD4QE8l5Z+kpsRUqrcnwLfKEfAmyMf96SoXmndZO/UyGMqDDrIno4lyj1uL9F0PMW86jjD X-Received: by 2002:a17:903:3091:b0:158:9f4c:a466 with SMTP id u17-20020a170903309100b001589f4ca466mr515142plc.169.1649798051845; Tue, 12 Apr 2022 14:14:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649798051; cv=none; d=google.com; s=arc-20160816; b=qhEMtLSEVDxneUmmM18cF8tAYOlJrRtZu1QPPM9lxrmQcMPiKthLosLVVD/L1wrJDD jpLl/fidfnNUx8Keq317glE3F+gqLfBrL34WNMvJCG8HDPltP/5+qGViGRHQrzGM+Q2w trvXdHyamkYNYHeTGM13sZne4WQO5cFA4+wefhNfWnuFhTocT1G6WvAPpl6Ci9r8hJLX V7ZJnaxTblq2srVz7Fy68O5wuP/ONhcNPRvvRI80gL8MbAztIN+rsBPtHfXwXbrcam7M WTzZuVEUEtbs5S13fNHrXhPYoRGclp6m9KOaEZvZBwbZDxOjzP10b9v4n92R/xOv7WAi YoBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:in-reply-to:subject :from:references:cc:to:content-language:user-agent:mime-version:date :message-id:dkim-signature; bh=I8ebi26NivgyfcxO6lfkcFEvhUg3Q8KsTVG3qn/kpMU=; b=TxGhXbFIuXLoKMGIXwYpskrTH3birF/bgoCb+jPkD9N0b37qM2U6a36so/ZnMYzzF2 d0dyGD18cwDwOGGRJepv/28mjPVFp0bDZuER6PfY0tJ9FuJR3xrhBZclDqD1voeHBZ7D cnDUNTlyg72tOeixHSEy/Cyv1/Ikjarr2DRwAojImwoAIMOHbbiat2WBgzgh4180/ufo 3+c6lXbbtXGkIT+QlQOy54lDCTD5SM3mYhgHbmiBKgALRnXmFXKdjdhRXYHawJ5CQM+M zTjW13zPkSJlAaF8fHB1wIKZZN6QFdLxnferBsxgTucGVtZxNQG5d3RPZ57wkTp2gkJX 2iLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=iniVuKkx; spf=softfail (google.com: domain of transitioning linux-kernel-owner@vger.kernel.org does not designate 23.128.96.19 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net. [23.128.96.19]) by mx.google.com with ESMTPS id x75-20020a63314e000000b0039daab0bc0asi1125932pgx.203.2022.04.12.14.14.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Apr 2022 14:14:11 -0700 (PDT) Received-SPF: softfail (google.com: domain of transitioning linux-kernel-owner@vger.kernel.org does not designate 23.128.96.19 as permitted sender) client-ip=23.128.96.19; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=iniVuKkx; spf=softfail (google.com: domain of transitioning linux-kernel-owner@vger.kernel.org does not designate 23.128.96.19 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 34A52ECC69; Tue, 12 Apr 2022 13:29:32 -0700 (PDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357108AbiDLPiO (ORCPT + 99 others); Tue, 12 Apr 2022 11:38:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45938 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357114AbiDLPiM (ORCPT ); Tue, 12 Apr 2022 11:38:12 -0400 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 778E1554A1 for ; Tue, 12 Apr 2022 08:35:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649777752; x=1681313752; h=message-id:date:mime-version:to:cc:references:from: subject:in-reply-to:content-transfer-encoding; bh=lj9QUXdM5GCMuPvK+BqdMIEkmXMFoN2VtIV9O9lZiCQ=; b=iniVuKkxRvTnQUOsODUFsiEQ0X3IH9yvSxQHt5ppDlaIXHBLxV12D4f0 lh3tPHiu740cetLhrI3kunqcdbycN0MPWA2aeReTWcZYJKBAhcQmO/ATe uv+ME/Np6e12UpnxeZRD4e8JrEZ04HOTDlA6rxgFyUayiBp/PX2ngpbQk gvDB2fgYah3/HBcHOcl1+nfJb8dLcFm7n9GHmmGp3UVJaAbFYYSL0inBF 46t3lKTDMaEh0AygoBi8esHs92ZLMfLKZ+LjyJzC1odCEn5t7lvgvv4FO m6CE7olpBIQq0Yg0IP3X11YnBj8XbYGx6MFzswio/1C4OqolbKpOxgP19 A==; X-IronPort-AV: E=McAfee;i="6400,9594,10315"; a="322847209" X-IronPort-AV: E=Sophos;i="5.90,254,1643702400"; d="scan'208";a="322847209" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2022 08:35:51 -0700 X-IronPort-AV: E=Sophos;i="5.90,254,1643702400"; d="scan'208";a="551758622" Received: from vtelkarx-mobl.amr.corp.intel.com (HELO [10.209.191.73]) ([10.209.191.73]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2022 08:35:50 -0700 Message-ID: <8b1e40c9-b2e8-7b73-d9ad-2c6a5a167370@intel.com> Date: Tue, 12 Apr 2022 08:35:56 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Content-Language: en-US To: Jean-Philippe Brucker Cc: "zhangfei.gao@foxmail.com" , Joerg Roedel , Fenghua Yu , Ravi V Shankar , Tony Luck , Ashok Raj , Peter Zijlstra , Dave Hansen , x86 , linux-kernel , iommu , Ingo Molnar , Borislav Petkov , Andy Lutomirski , Josh Poimboeuf , Thomas Gleixner References: <20220207230254.3342514-6-fenghua.yu@intel.com> <56ed509d-a7cf-1fde-676c-a28eb204989b@intel.com> <41ed3405-66d9-0cde-fc01-b3eacb85a081@intel.com> From: Dave Hansen Subject: Re: [PATCH v4 05/11] iommu/sva: Assign a PASID to mm on PASID allocation and free it on mm exit In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-3.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,NICE_REPLY_A,RDNS_NONE,SPF_HELO_NONE, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 4/12/22 08:10, Jean-Philippe Brucker wrote: >> I wonder if the Intel and ARM IOMMU code differ in the way they keep >> references to the mm, or if this affects Intel as well, but we just >> haven't tested the code enough. > The Arm code was written expecting the PASID to be freed on unbind(), not > mm exit. I missed the change of behavior, sorry (I thought your plan was > to extend PASID lifetime, not shorten it?) but as is it seems very broken. > For example in the iommu_sva_unbind_device(), we have > arm_smmu_mmu_notifier_put() clearing the PASID table entry for > "mm->pasid", which is going to end badly if the PASID has been cleared or > reallocated. We can't clear the PASID entry in mm exit because at that > point the device may still be issuing DMA for that PASID and we need to > quiesce the entry rather than deactivate it. I think we ended up flipping some of this around on the Intel side. Instead of having to quiesce the device on mm exit, we don't let the mm exit until the device is done. When you program the pasid into the device, it's a lot like when you create a thread. We bump the reference count on the mm when we program the page table pointer into a CPU. We drop the thread's reference to the mm when the thread exits and will no longer be using the page tables. Same thing with pasids. We bump the refcount on the mm when the pasid is programmed into the device. Once the device is done with the mm, we drop the mm. Basically, instead of recounting the pasid itself, we just refcount the mm.