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From:   Tim Harvey <tharvey@gateworks.com>
Date:   Mon, 11 Apr 2022 12:44:23 -0700
Message-ID: <CAJ+vNU0VVpDGDXivz=r8C4U8dYjA08SqnzPXwmtOv4ujvc3=Zg@mail.gmail.com>
Subject: Re: [PATCH] imx8mm-venice-gw7902: update pci refclk
To:     Shawn Guo <shawnguo@kernel.org>
Cc:     Rob Herring <robh+dt@kernel.org>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        Pengutronix Kernel Team <kernel@pengutronix.de>,
        Fabio Estevam <festevam@gmail.com>,
        NXP Linux Team <linux-imx@nxp.com>,
        Device Tree Mailing List <devicetree@vger.kernel.org>,
        Linux ARM Mailing List <linux-arm-kernel@lists.infradead.org>,
        open list <linux-kernel@vger.kernel.org>
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On Sun, Apr 10, 2022 at 6:31 PM Shawn Guo <shawnguo@kernel.org> wrote:
>
> On Tue, Apr 05, 2022 at 01:06:25PM -0700, Tim Harvey wrote:
> > Use the correct PCI clock bindings.
>
> Please improve the commit log to explain why clock "pcie_phy" can be
> dropped.
>

Shawn,

The original PCIe bindings for this board were wrong - they were from
a version of the bindings that was not yet approved (my mistake) and
I'm just trying to bring them up to date.

That said, I looked at the latest fsl,imx6q-pcie.yaml dt-bindings [1]
and see that there should be a min of 3 clocks called 'pcie',
'pcie_bus', and 'pcie_phy'. However I notice that all of the current
imx8mm boards that enable PCI have clock-names of 'pcie', 'pcie_aux',
and 'pcie_bus'. It seems like all the imx8mm boards having pcie have
clock-names this way:

arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts

Does the binding need to change or do the clock names need to change
in the above?

Best Regards,

Tim
[1]

> Shawn
>
> >
> > Signed-off-by: Tim Harvey <tharvey@gateworks.com>
> > ---
> >  arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts | 6 +++---
> >  1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
> > index 6aa0eb463647..f71416be29a7 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
> > @@ -595,7 +595,7 @@
> >  &pcie_phy {
> >       fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
> >       fsl,clkreq-unsupported;
> > -     clocks = <&clk IMX8MM_CLK_DUMMY>;
> > +     clocks = <&pcie0_refclk>;
> >       status = "okay";
> >  };
> >
> > @@ -604,8 +604,8 @@
> >       pinctrl-0 = <&pinctrl_pcie0>;
> >       reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
> >       clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
> > -              <&clk IMX8MM_CLK_DUMMY>, <&pcie0_refclk>;
> > -     clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
> > +              <&pcie0_refclk>;
> > +     clock-names = "pcie", "pcie_aux", "pcie_bus";
> >       assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
> >                         <&clk IMX8MM_CLK_PCIE1_CTRL>;
> >       assigned-clock-rates = <10000000>, <250000000>;
> > --
> > 2.17.1
> >