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Message-ID: <86a07099-1074-e8d1-6d0e-1ce68414b627@ideasonboard.com>
Date:   Tue, 12 Apr 2022 17:24:58 +0300
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Subject: Re: [PATCH] drm/tidss: Soft Reset DISPC on startup
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To:     Devarsh Thakkar <devarsht@ti.com>, linux-kernel@vger.kernel.org,
        jyri.sarha@iki.fi, tomba@kernel.org, airlied@linux.ie,
        daniel@ffwll.ch, dri-devel@lists.freedesktop.org
Cc:     nm@ti.com, a-bhatia1@ti.com, r-ravikumar@ti.com, nikhil.nd@ti.com,
        linux-arm-kernel@lists.infradead.org, vigneshr@ti.com,
        laurent.pinchart@ideasonboard.com
References: <20220314113739.18000-1-devarsht@ti.com>
From:   Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
In-Reply-To: <20220314113739.18000-1-devarsht@ti.com>
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Hi,

On 14/03/2022 13:37, Devarsh Thakkar wrote:
> Soft reset the display subsystem controller on startup and wait for
> the reset to complete. This helps the scenario where display was
> already in use by some other core before the linux was booted.

The reason the omapdrm doesn't do a reset is that the PM features on 
some of the DSS registers were set and controlled outside dss driver, so 
the dss driver could not do a reset just like that. That design was 
carried to the tidss driver, although I'm not sure if the reason is 
valid on AM6 and J7 platforms.

If that reasoning is not valid, this patch is ok and:

Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>

  Tomi

> Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
> ---
>   drivers/gpu/drm/tidss/tidss_dispc.c | 18 ++++++++++++++++++
>   1 file changed, 18 insertions(+)
> 
> diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c
> index 60b92df615aa..dae47853b728 100644
> --- a/drivers/gpu/drm/tidss/tidss_dispc.c
> +++ b/drivers/gpu/drm/tidss/tidss_dispc.c
> @@ -2650,6 +2650,20 @@ static void dispc_init_errata(struct dispc_device *dispc)
>   	}
>   }
>   
> +static void dispc_softreset(struct dispc_device *dispc)
> +{
> +	u32 val;
> +	int ret = 0;
> +
> +	/* Soft reset */
> +	REG_FLD_MOD(dispc, DSS_SYSCONFIG, 1, 1, 1);
> +	/* Wait for reset to complete */
> +	ret = readl_poll_timeout(dispc->base_common + DSS_SYSSTATUS,
> +				 val, val & 1, 100, 5000);
> +	if (ret)
> +		dev_warn(dispc->dev, "failed to reset dispc\n");
> +}
> +
>   int dispc_init(struct tidss_device *tidss)
>   {
>   	struct device *dev = tidss->dev;
> @@ -2709,6 +2723,10 @@ int dispc_init(struct tidss_device *tidss)
>   			return r;
>   	}
>   
> +	/* K2G display controller does not support soft reset */
> +	if (feat->subrev != DISPC_K2G)
> +		dispc_softreset(dispc);
> +
>   	for (i = 0; i < dispc->feat->num_vps; i++) {
>   		u32 gamma_size = dispc->feat->vp_feat.color.gamma_size;
>   		u32 *gamma_table;