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Date:   Tue, 12 Apr 2022 13:54:11 -0700
From:   Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
To:     Jon Kohler <jon@nutanix.com>
Cc:     Thomas Gleixner <tglx@linutronix.de>,
        Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
        Dave Hansen <dave.hansen@linux.intel.com>, x86@kernel.org,
        "H. Peter Anvin" <hpa@zytor.com>, Andi Kleen <ak@linux.intel.com>,
        Tony Luck <tony.luck@intel.com>, linux-kernel@vger.kernel.org,
        dave.hansen@intel.com, Borislav Petkov <bp@suse.de>,
        Neelima Krishnan <neelima.krishnan@intel.com>,
        "kvm @ vger . kernel . org" <kvm@vger.kernel.org>
Subject: Re: [PATCH v2] x86/tsx: fix KVM guest live migration for tsx=on
Message-ID: <20220412205411.m7n2gnon3ai7wobm@guptapa-desk>
References: <20220411180131.5054-1-jon@nutanix.com>
 <20220411200703.48654-1-jon@nutanix.com>
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On Mon, Apr 11, 2022 at 04:07:01PM -0400, Jon Kohler wrote:
>Move automatic disablement for TSX microcode deprecation from tsx_init() to
>x86_get_tsx_auto_mode(), such that systems with tsx=on will continue to
>see the TSX CPU features (HLE, RTM) even on updated microcode.
>
>KVM live migration could be possibly be broken in 5.14+ commit 293649307ef9
>("x86/tsx: Clear CPUID bits when TSX always force aborts"). Consider the
>following scenario:
>
>1. KVM hosts clustered in a live migration capable setup.
>2. KVM guests have TSX CPU features HLE and/or RTM presented.
>3. One of the three maintenance events occur:
>3a. An existing host running kernel >= 5.14 in the pool updated with the
>    new microcode.
>3b. A new host running kernel >= 5.14 is commissioned that already has the
>    microcode update preloaded.
>3c. All hosts are running kernel < 5.14 with microcode update already
>    loaded and one existing host gets updated to kernel >= 5.14.
>4. After maintenance event, the impacted host will not have HLE and RTM
>   exposed, and live migrations with guests with TSX features might not
>   migrate.

Which part was this reproduced on? AFAIK server parts(except for some
Intel Xeon E3s) did not get such microcode update.

Thanks,
Pawan