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[2620:137:e000::1:18]) by mx.google.com with ESMTPS id x12-20020a65538c000000b0039d59a0d9a2si4383511pgq.412.2022.04.12.17.11.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Apr 2022 17:11:04 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:18 as permitted sender) client-ip=2620:137:e000::1:18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=kqBrKtUi; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:18 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id B6886141D9F; Tue, 12 Apr 2022 15:25:30 -0700 (PDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356582AbiDLTH6 (ORCPT + 99 others); Tue, 12 Apr 2022 15:07:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49152 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1355179AbiDLTHy (ORCPT ); Tue, 12 Apr 2022 15:07:54 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 656C5419A0; Tue, 12 Apr 2022 12:05:36 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id AC93561B5D; Tue, 12 Apr 2022 19:05:35 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 092A1C385A5; Tue, 12 Apr 2022 19:05:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1649790335; bh=ZbSkaC5MBfF62iamJnsXlTvwu8C3ghdAlvLgcGBAFjo=; h=In-Reply-To:References:Subject:From:Cc:To:Date:From; b=kqBrKtUiARnFtFQ4c56T+sZHxkMznV0/BHbnW0R3BzLCLsIwLkw/macH4R4XL6GGQ cLSTuq75Gf0TfAXsz/nrYkfGBISUsBWa2jBuPDlhtJcWq2m4omI2LZQPnwR+wAp//r VApgztD69V7jhEf1/4tUeve7dDegd1saJntevQn2zZZuOXx+is5a+sdjDJKvIRLAoS nc74datHUPpbeHcgDQJuLcKpiWNPtPV+cSO+J3cOIrt3516Ke7TWMbzvzN/5NlFPFr 51ofQynDkxS8vMaj7x1ce/1c4l5ZK0/XG/sLysQP9eLi8PS/8yI/QJyO9RluiBtHSZ CctreOpAWwA/Q== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable In-Reply-To: <20220408224321.627126-2-bjorn.andersson@linaro.org> References: <20220408224321.627126-1-bjorn.andersson@linaro.org> <20220408224321.627126-2-bjorn.andersson@linaro.org> Subject: Re: [PATCH 2/2] clk: qcom: add sc8280xp GCC driver From: Stephen Boyd Cc: Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org To: Bjorn Andersson , Michael Turquette Date: Tue, 12 Apr 2022 12:05:33 -0700 User-Agent: alot/0.10 Message-Id: <20220412190535.092A1C385A5@smtp.kernel.org> X-Spam-Status: No, score=-2.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,MAILING_LIST_MULTI, RDNS_NONE,SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Quoting Bjorn Andersson (2022-04-08 15:43:21) > diff --git a/drivers/clk/qcom/gcc-sc8280xp.c b/drivers/clk/qcom/gcc-sc828= 0xp.c > new file mode 100644 > index 000000000000..e621a25a4a40 > --- /dev/null > +++ b/drivers/clk/qcom/gcc-sc8280xp.c > @@ -0,0 +1,7463 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) 2021, The Linux Foundation. All rights reserved. > + * Copyright (c) 2022, Linaro Ltd. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > + > +#include "clk-alpha-pll.h" > +#include "clk-branch.h" [...] > + > +static struct clk_alpha_pll gcc_gpll0 =3D { > + .offset =3D 0x0, > + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], > + .clkr =3D { > + .enable_reg =3D 0x52028, > + .enable_mask =3D BIT(0), > + .hw.init =3D &(struct clk_init_data){ const > + .name =3D "gcc_gpll0", > + .parent_data =3D &(const struct clk_parent_data){ > + .fw_name =3D "bi_tcxo", This can't be shared for multiple PLLs? > + }, > + .num_parents =3D 1, > + .ops =3D &clk_alpha_pll_fixed_lucid_5lpe_ops, > + }, > + }, > +}; > +