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Message-ID: <0cf83ec0-29d3-fbde-0b7d-9d58d210f0a4@rock-chips.com>
Date:   Wed, 13 Apr 2022 10:54:45 +0800
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Cc:     shawn.lin@rock-chips.com, linux-rockchip@lists.infradead.org,
        linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1 2/4] PCI: dwc: rockchip: add legacy interrupt support
Content-Language: en-GB
To:     Peter Geis <pgwipeout@gmail.com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
        Rob Herring <robh@kernel.org>,
        =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= <kw@linux.com>,
        Bjorn Helgaas <bhelgaas@google.com>,
        Heiko Stuebner <heiko@sntech.de>
References: <20220412185751.124783-1-pgwipeout@gmail.com>
 <20220412185751.124783-3-pgwipeout@gmail.com>
From:   Shawn Lin <shawn.lin@rock-chips.com>
In-Reply-To: <20220412185751.124783-3-pgwipeout@gmail.com>
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Hi Peter,

在 2022/4/13 2:57, Peter Geis 写道:
> The legacy interrupts on the rk356x pcie controller are handled by a
> single muxed interrupt. Add irq domain support to the pcie-dw-rockchip >
> +static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
> +{
> +	struct irq_chip *chip = irq_desc_get_chip(desc);
> +	struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc);
> +	struct device *dev = rockchip->pci.dev;
> +	u32 reg;
> +	u32 hwirq;
> +	u32 virq;
> +
> +	chained_irq_enter(chip, desc);
> +
> +	reg = rockchip_pcie_readl_apb(rockchip, 0x8);
> +


Overall it looks good except that 0x8 has a name,
PCIE_CLIENT_INTR_STATUS_LEGACY. BTW, If you consider adding more support
to it, for instance, enable/disable/affinity?  The downstream kernel
finished these for better fitting for function driver usage.