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Peter Anvin" CC: , , , Kefeng Wang , Xie XiuQi References: <20220412072552.2526871-1-tongtiangen@huawei.com> <20220412072552.2526871-5-tongtiangen@huawei.com> <38c6d4b5-a3db-5c3e-02e7-39875edb3476@arm.com> From: Tong Tiangen In-Reply-To: <38c6d4b5-a3db-5c3e-02e7-39875edb3476@arm.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.174.179.234] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To kwepemm600017.china.huawei.com (7.193.23.234) X-CFilter-Loop: Reflected X-Spam-Status: No, score=-5.5 required=5.0 tests=BAYES_00,NICE_REPLY_A, RCVD_IN_DNSWL_MED,RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 在 2022/4/13 1:08, Robin Murphy 写道: > On 12/04/2022 8:25 am, Tong Tiangen wrote: > [...] >> diff --git a/arch/arm64/include/asm/asm-uaccess.h >> b/arch/arm64/include/asm/asm-uaccess.h >> index 0557af834e03..bb17f0829042 100644 >> --- a/arch/arm64/include/asm/asm-uaccess.h >> +++ b/arch/arm64/include/asm/asm-uaccess.h >> @@ -92,4 +92,20 @@ alternative_else_nop_endif >>           _asm_extable    8888b,\l; >>       .endm >> + >> +    .macro user_ldp_mc l, reg1, reg2, addr, post_inc >> +8888:        ldtr    \reg1, [\addr]; >> +8889:        ldtr    \reg2, [\addr, #8]; >> +        add    \addr, \addr, \post_inc; >> + >> +        _asm_extable_uaccess_mc    8888b, \l; >> +        _asm_extable_uaccess_mc    8889b, \l; >> +    .endm > > You're replacing the only user of this, so please just > s/_asm_extable/_asm_extable_uaccess_mc/ in the existing macro and save > the rest of the churn. > > Furthermore, how come you're not similarly updating user_stp, given that > you *are* updating the other stores in copy_to_user? I think all load/store instructions should be handled. Generally speaking, the load operation will receive a sea when consuming a hardware memory error, and the store operation will not receive a sea when consuming a hardware error. Depends on chip behavior. So add store class instructions to processed is no harm. If there is any problem with my understanding, correct me. Thanks, Tong. > >> + >> +    .macro user_ldst_mc l, inst, reg, addr, post_inc >> +8888:        \inst        \reg, [\addr]; >> +        add        \addr, \addr, \post_inc; >> + >> +        _asm_extable_uaccess_mc    8888b, \l; >> +    .endm > [...]