Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Date:   Wed, 13 Apr 2022 15:27:03 +0530
From:   Vinod Koul <vkoul@kernel.org>
To:     Swapnil Jakhade <sjakhade@cadence.com>
Cc:     kishon@ti.com, linux-phy@lists.infradead.org,
        linux-kernel@vger.kernel.org, mparab@cadence.com,
        a-govindraju@ti.com
Subject: Re: [PATCH] phy: cadence: Sierra: Add TI J721E specific PCIe
 multilink lane configuration
Message-ID: <Ylaeb1169qh/Nx5D@matsya>
References: <20220303055026.24899-1-sjakhade@cadence.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <20220303055026.24899-1-sjakhade@cadence.com>
Precedence: bulk

On 03-03-22, 06:50, Swapnil Jakhade wrote:
> This patch adds workaround for TI J721E errata i2183
> (https://www.ti.com/lit/er/sprz455a/sprz455a.pdf).
> PCIe fails to link up if SERDES lanes not used by PCIe are assigned to
> another protocol. For example, link training fails if lanes 2 and 3 are
> assigned to another protocol while lanes 0 and 1 are used for PCIe to
> form a two lane link. This failure is due to an incorrect tie-off on an
> internal status signal indicating electrical idle.
> 
> Status signals going from SERDES to PCIe Controller are tied-off when a
> lane is not assigned to PCIe. Signal indicating electrical idle is
> incorrectly tied-off to a state that indicates non-idle. As a result,
> PCIe sees unused lanes to be out of electrical idle and this causes
> LTSSM to exit Detect.Quiet state without waiting for 12ms timeout to
> occur. If a receiver is not detected on the first receiver detection
> attempt in Detect.Active state, LTSSM goes back to Detect.Quiet and
> again moves forward to Detect.Active state without waiting for 12ms as
> required by PCIe base specification. Since wait time in Detect.Quiet is
> skipped, multiple receiver detect operations are performed back-to-back
> without allowing time for capacitance on the transmit lines to
> discharge. This causes subsequent receiver detection to always fail even
> if a receiver gets connected eventually.
> 
> The workaround only works for 1-lane PCIe configuration. This workaround
> involves enabling receiver detect override by setting TX_RCVDET_OVRD_PREG_j
> register of the lane running PCIe to 0x2. This causes SERDES to indicate
> successful receiver detect when LTSSM is in Detect.Active state, whether a
> receiver is actually present or not. If the receiver is present, LTSSM
> proceeds to link up as expected. However if receiver is not present, LTSSM
> will time out in Polling.Configuration substate since the expected training
> sequence packets will not be received.

Applied, thanks

-- 
~Vinod