Received: by 2002:a05:6a10:6d10:0:0:0:0 with SMTP id gq16csp750569pxb; Wed, 13 Apr 2022 11:30:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy3GLVgwA9a6yagSo93FysIpq1WAfbupgjApR4q1VoKPWV964DdDgGg9ZiFBn0/FM6Jvcsz X-Received: by 2002:a17:902:e0c9:b0:158:2dda:40d8 with SMTP id e9-20020a170902e0c900b001582dda40d8mr24409881pla.165.1649874610950; Wed, 13 Apr 2022 11:30:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649874610; cv=none; d=google.com; s=arc-20160816; b=vwCgt+vfK0mU6DSa5vTYJ6LMgeOHK+SqKSHZ2LBKEnj7SReMngx6yxhAe3RdjLmlqA Nwa+4uwYGGkYx+pp4H2sNMMSswmv9TO8xLITLCm8qx74N/X8n3R0wPNzCTkbkY2AbObN D5DFo/YJn089vncBg2kgmQuLQBFqlCtLFMJ2M6vJSm/0f1oCrxuGbWSl39j9OD+92kRj XrvkhXL8SFq+mmoSBdRKcOD08tNJ2r2LrzKWgWiyjugtOerVvtP9ZnKzI41iYT3Nx0aI 9wW21BzwbmZ/Yhym+11M2mxrbgFmBuI7HsA/mlZ6Ss0MxGmt//2x1garDuoXvHYLg19b ZVcg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=Vl6SQiy5vu9EZTWkVBhNnZBEyiT+stKz3fv32aZTWs0=; b=NM0NYwjOaDgXZj6hJhIPpuS5rMb3ZUh4q8mSt3TmBzni6Up28OcWokhLUJHfTmezTZ fgMKZSXBl5XlM3R8z7OCKjLDz3bxIbMhBZle2gbAKIowFYXoyoAMaD+++eYlAQPhFHJ8 4ua3iQpH7WVOKUzuyBDEuglKytAIMrDVgsv+031Zoi4/M6rxfmTWfRtHnNh4GJBh4pz9 oM3SwfZMJR7NvW2sFdb6dTNPDsUaMwiNhKJjk4Nc9XFIh6bb0yRgimrNKbddWos2X6Ou 4p4yg9Y7D0m45FFYVaV1xafIUw4u8p3qxk6yfw3d9jWVJdtlHD9sUOXoxQ2Q5IMpOLp5 pbyg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=bxlBvB6n; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id k123-20020a636f81000000b0039958d09337si6547191pgc.280.2022.04.13.11.29.55; Wed, 13 Apr 2022 11:30:10 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=bxlBvB6n; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231704AbiDMNj0 (ORCPT + 99 others); Wed, 13 Apr 2022 09:39:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47386 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231599AbiDMNjX (ORCPT ); Wed, 13 Apr 2022 09:39:23 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DEC0C5F240; Wed, 13 Apr 2022 06:37:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649857021; x=1681393021; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=Vl6SQiy5vu9EZTWkVBhNnZBEyiT+stKz3fv32aZTWs0=; b=bxlBvB6nfaS2ovpRpaIxWlnyRshBBWJ/KzHkAUPjJYrxr55A6b8yhfX/ QFQDXuFBjkTGEqpSEgbC+j9t2q9GvUsjzX+1cvfMS9dmgluqxb9CvM5W0 PHiWu+Vi4zoZDgrthNFqyvaytqB3DDlf/5EPkTARUV5bxGXtu412oC4Qp I=; Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-02.qualcomm.com with ESMTP; 13 Apr 2022 06:37:01 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-SD-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2022 06:37:01 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 13 Apr 2022 06:36:40 -0700 Received: from jhugo-lnx.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 13 Apr 2022 06:36:39 -0700 From: Jeffrey Hugo To: , , , , , , , , , CC: , , , , Jeffrey Hugo Subject: [PATCH v2] PCI: hv: Fix multi-MSI to allow more than one MSI vector Date: Wed, 13 Apr 2022 07:36:21 -0600 Message-ID: <1649856981-14649-1-git-send-email-quic_jhugo@quicinc.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org If the allocation of multiple MSI vectors for multi-MSI fails in the core PCI framework, the framework will retry the allocation as a single MSI vector, assuming that meets the min_vecs specified by the requesting driver. Hyper-V advertises that multi-MSI is supported, but reuses the VECTOR domain to implement that for x86. The VECTOR domain does not support multi-MSI, so the alloc will always fail and fallback to a single MSI allocation. In short, Hyper-V advertises a capability it does not implement. Hyper-V can support multi-MSI because it coordinates with the hypervisor to map the MSIs in the IOMMU's interrupt remapper, which is something the VECTOR domain does not have. Therefore the fix is simple - copy what the x86 IOMMU drivers (AMD/Intel-IR) do by removing X86_IRQ_ALLOC_CONTIGUOUS_VECTORS after calling the VECTOR domain's pci_msi_prepare(). Fixes: 4daace0d8ce8 ("PCI: hv: Add paravirtual PCI front-end for Microsoft Hyper-V VMs") Signed-off-by: Jeffrey Hugo Reviewed-by: Dexuan Cui --- v2: -Fix grammatical mistake in added comment drivers/pci/controller/pci-hyperv.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pci-hyperv.c b/drivers/pci/controller/pci-hyperv.c index d270a204..1cbe24b 100644 --- a/drivers/pci/controller/pci-hyperv.c +++ b/drivers/pci/controller/pci-hyperv.c @@ -614,7 +614,16 @@ static void hv_set_msi_entry_from_desc(union hv_msi_entry *msi_entry, static int hv_msi_prepare(struct irq_domain *domain, struct device *dev, int nvec, msi_alloc_info_t *info) { - return pci_msi_prepare(domain, dev, nvec, info); + int ret = pci_msi_prepare(domain, dev, nvec, info); + + /* + * By using the interrupt remapper in the hypervisor IOMMU, contiguous + * CPU vectors is not needed for multi-MSI + */ + if (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI) + info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS; + + return ret; } /** -- 2.7.4