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From:   Chuanhong Guo <gch981213@gmail.com>
Date:   Wed, 13 Apr 2022 13:07:32 +0800
Message-ID: <CAJsYDV++V0HCNqM-GnpBBwDjwBSfgw8ZO56wDwD3iMPJ4joSvg@mail.gmail.com>
Subject: Re: [PATCH] mtd: spinand: add support for ESMT F50x1G41LB
To:     linux-mtd@lists.infradead.org
Cc:     Miquel Raynal <miquel.raynal@bootlin.com>,
        Richard Weinberger <richard@nod.at>,
        Vignesh Raghavendra <vigneshr@ti.com>,
        Patrice Chotard <patrice.chotard@foss.st.com>,
        Boris Brezillon <boris.brezillon@collabora.com>,
        Christophe Kerello <christophe.kerello@foss.st.com>,
        Daniel Palmer <daniel@0x0f.com>,
        open list <linux-kernel@vger.kernel.org>
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On Wed, Apr 13, 2022 at 12:23 PM Chuanhong Guo <gch981213@gmail.com> wrote:
>
> This patch adds support for ESMT F50L1G41LB and F50D1G41LB.
> It seems that ESMT likes to use random JEDEC ID from other vendors.
> Their 1G chips uses 0xc8 from GigaDevice and 2G/4G chips uses 0x2c from
> Micron. For this reason, the ESMT entry is named esmt_c8 with explicit
> JEDEC ID in variable name.
>
> Datasheets:
> https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/F50L1G41LB(2M).pdf
> https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/F50D1G41LB(2M).pdf
>
> Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
> [...]
> +static const struct spinand_info esmt_c8_spinand_table[] = {
> +       SPINAND_INFO("F50L1G41LB",
> +                    SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x01, 0x7f,
> +                               0x7f, 0x7f),

This patch is broken. SPI NAND core doesn't support 5-byte ID atm.

-- 
Regards,
Chuanhong Guo