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From:   Leo Li <leoyang.li@nxp.com>
To:     Vladimir Oltean <olteanv@gmail.com>,
        "Z.Q. Hou" <zhiqiang.hou@nxp.com>
CC:     Shawn Guo <shawnguo@kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Xiaowei Bao <xiaowei.bao@nxp.com>
Subject: RE: [PATCH v3 1/8] arm64: dts: ls1028a: Add PCIe EP nodes
Thread-Topic: [PATCH v3 1/8] arm64: dts: ls1028a: Add PCIe EP nodes
Thread-Index: AQHX8M2PMjnmeEe/+EahWZj9h1xp0Kzuxm+AgAAXPtA=
Date:   Wed, 13 Apr 2022 18:03:37 +0000
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> -----Original Message-----
> From: Vladimir Oltean <olteanv@gmail.com>
> Sent: Wednesday, April 13, 2022 11:32 AM
> To: Leo Li <leoyang.li@nxp.com>
> Cc: Shawn Guo <shawnguo@kernel.org>; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org; Xiaowei Bao
> <xiaowei.bao@nxp.com>
> Subject: Re: [PATCH v3 1/8] arm64: dts: ls1028a: Add PCIe EP nodes
>=20
> On Tue, Dec 14, 2021 at 03:32:33AM -0600, Li Yang wrote:
> > From: Xiaowei Bao <xiaowei.bao@nxp.com>
> >
> > Add PCIe EP nodes for ls1028a to support EP mode.
> >
> > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> > Signed-off-by: Li Yang <leoyang.li@nxp.com>
> > ---
> >  .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 24
> > +++++++++++++++++++
> >  1 file changed, 24 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > index fd3f3e8bb6ce..9010c535252a 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > @@ -637,6 +637,18 @@ pcie1: pcie@3400000 {
> >  			status =3D "disabled";
> >  		};
> >
> > +		pcie_ep1: pcie-ep@3400000 {
> > +			compatible =3D "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep";
> > +			reg =3D <0x00 0x03400000 0x0 0x00100000
> > +			       0x80 0x00000000 0x8 0x00000000>;
> > +			reg-names =3D "regs", "addr_space";
> > +			interrupts =3D <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
> /* PME interrupt */
> > +			interrupt-names =3D "pme";
> > +			num-ib-windows =3D <6>;
> > +			num-ob-windows =3D <8>;
> > +			status =3D "disabled";
> > +		};
> > +
> >  		pcie2: pcie@3500000 {
> >  			compatible =3D "fsl,ls1028a-pcie";
> >  			reg =3D <0x00 0x03500000 0x0 0x00100000>, /*
> controller registers */
> > @@ -664,6 +676,18 @@ pcie2: pcie@3500000 {
> >  			status =3D "disabled";
> >  		};
> >
> > +		pcie_ep2: pcie-ep@3500000 {
> > +			compatible =3D "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep";
> > +			reg =3D <0x00 0x03500000 0x0 0x00100000
> > +			       0x88 0x00000000 0x8 0x00000000>;
> > +			reg-names =3D "regs", "addr_space";
> > +			interrupts =3D <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
> /* PME interrupt */
> > +			interrupt-names =3D "pme";
> > +			num-ib-windows =3D <6>;
> > +			num-ob-windows =3D <8>;
> > +			status =3D "disabled";
> > +		};
> > +
> >  		smmu: iommu@5000000 {
> >  			compatible =3D "arm,mmu-500";
> >  			reg =3D <0 0x5000000 0 0x800000>;
> > --
> > 2.25.1
> >
>=20
> arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi:631.23-656.5: Warning
> (unique_unit_address): /soc/pcie@3400000: duplicate unit-address (also
> used in node /soc/pcie-ep@3400000)
> arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi:670.23-695.5: Warning
> (unique_unit_address): /soc/pcie@3500000: duplicate unit-address (also
> used in node /soc/pcie-ep@3500000)

This would be a common problem for all the layerscape PCIe controller.  The=
 controller can either work in RC mode or EP mode.  The current binding of =
the controller defined two compatibles, one for RC and one for EP.  Therefo=
re the SoC dtsi will have two nodes with the same unit address one for EP o=
ne for RC.  Fixing this probably requires comprehensive updates to the bind=
ing which breaks backward compatibility.

Regards,
Leo