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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DU2PR04MB8949.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6c51e8d8-2fe5-465b-319f-08da1d77eedd X-MS-Exchange-CrossTenant-originalarrivaltime: 13 Apr 2022 18:03:37.0713 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: wUqcncZzEUvZOt07ec085PcPaw2B/GSwr9TKJKuPlIjD29CU4R40o6zj50+1DJLn46rsTKgdHH6wTgyvIg9CFA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR04MB8214 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: Vladimir Oltean > Sent: Wednesday, April 13, 2022 11:32 AM > To: Leo Li > Cc: Shawn Guo ; linux-arm- > kernel@lists.infradead.org; linux-kernel@vger.kernel.org; Xiaowei Bao > > Subject: Re: [PATCH v3 1/8] arm64: dts: ls1028a: Add PCIe EP nodes >=20 > On Tue, Dec 14, 2021 at 03:32:33AM -0600, Li Yang wrote: > > From: Xiaowei Bao > > > > Add PCIe EP nodes for ls1028a to support EP mode. > > > > Signed-off-by: Xiaowei Bao > > Signed-off-by: Li Yang > > --- > > .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 24 > > +++++++++++++++++++ > > 1 file changed, 24 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi > > b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi > > index fd3f3e8bb6ce..9010c535252a 100644 > > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi > > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi > > @@ -637,6 +637,18 @@ pcie1: pcie@3400000 { > > status =3D "disabled"; > > }; > > > > + pcie_ep1: pcie-ep@3400000 { > > + compatible =3D "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep"; > > + reg =3D <0x00 0x03400000 0x0 0x00100000 > > + 0x80 0x00000000 0x8 0x00000000>; > > + reg-names =3D "regs", "addr_space"; > > + interrupts =3D ; > /* PME interrupt */ > > + interrupt-names =3D "pme"; > > + num-ib-windows =3D <6>; > > + num-ob-windows =3D <8>; > > + status =3D "disabled"; > > + }; > > + > > pcie2: pcie@3500000 { > > compatible =3D "fsl,ls1028a-pcie"; > > reg =3D <0x00 0x03500000 0x0 0x00100000>, /* > controller registers */ > > @@ -664,6 +676,18 @@ pcie2: pcie@3500000 { > > status =3D "disabled"; > > }; > > > > + pcie_ep2: pcie-ep@3500000 { > > + compatible =3D "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep"; > > + reg =3D <0x00 0x03500000 0x0 0x00100000 > > + 0x88 0x00000000 0x8 0x00000000>; > > + reg-names =3D "regs", "addr_space"; > > + interrupts =3D ; > /* PME interrupt */ > > + interrupt-names =3D "pme"; > > + num-ib-windows =3D <6>; > > + num-ob-windows =3D <8>; > > + status =3D "disabled"; > > + }; > > + > > smmu: iommu@5000000 { > > compatible =3D "arm,mmu-500"; > > reg =3D <0 0x5000000 0 0x800000>; > > -- > > 2.25.1 > > >=20 > arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi:631.23-656.5: Warning > (unique_unit_address): /soc/pcie@3400000: duplicate unit-address (also > used in node /soc/pcie-ep@3400000) > arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi:670.23-695.5: Warning > (unique_unit_address): /soc/pcie@3500000: duplicate unit-address (also > used in node /soc/pcie-ep@3500000) This would be a common problem for all the layerscape PCIe controller. The= controller can either work in RC mode or EP mode. The current binding of = the controller defined two compatibles, one for RC and one for EP. Therefo= re the SoC dtsi will have two nodes with the same unit address one for EP o= ne for RC. Fixing this probably requires comprehensive updates to the bind= ing which breaks backward compatibility. Regards, Leo