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Received: from AM7PR04MB7046.eurprd04.prod.outlook.com (2603:10a6:20b:113::22) by AM6PR04MB5782.eurprd04.prod.outlook.com (2603:10a6:20b:aa::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5144.30; Thu, 14 Apr 2022 06:35:41 +0000 Received: from AM7PR04MB7046.eurprd04.prod.outlook.com ([fe80::b09c:8ffe:8e02:7387]) by AM7PR04MB7046.eurprd04.prod.outlook.com ([fe80::b09c:8ffe:8e02:7387%9]) with mapi id 15.20.5164.018; Thu, 14 Apr 2022 06:35:41 +0000 Message-ID: <1bd1ab210eae96fdd0280b9ef6876ae918d48cb3.camel@nxp.com> Subject: Re: [PATCH v6 resend 2/5] phy: Add LVDS configuration options From: Liu Ying To: Vinod Koul Cc: linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, kishon@ti.com, robh+dt@kernel.org, andrzej.hajda@intel.com, narmstrong@baylibre.com, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, airlied@linux.ie, daniel@ffwll.ch, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, agx@sigxcpu.org, robert.chiras@nxp.com, martin.kepplinger@puri.sm, robert.foss@linaro.org Date: Thu, 14 Apr 2022 14:35:29 +0800 In-Reply-To: References: <20220402052451.2517469-1-victor.liu@nxp.com> <20220402052451.2517469-3-victor.liu@nxp.com> Content-Type: text/plain; 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The set of parameters > > > > > > should cover all potential users. > > > > > > > > > > > > Cc: Kishon Vijay Abraham I > > > > > > Cc: Vinod Koul > > > > > > Cc: NXP Linux Team > > > > > > Signed-off-by: Liu Ying > > > > > > --- > > > > [...] > > > > > > > > + */ > > > > > > + > > > > > > +#ifndef __PHY_LVDS_H_ > > > > > > +#define __PHY_LVDS_H_ > > > > > > + > > > > > > +/** > > > > > > + * struct phy_configure_opts_lvds - LVDS configuration set > > > > > > + * @bits_per_lane_and_dclk_cycle: Number of bits per data > > > > > > lane > > > > > > and > > > > > > + * differential clock > > > > > > cycle. > > > > > > > > > > What does it mean by bits per data lane and differential > > > > > clock > > > > > cycle? > > > > > > > > Please check > > > > Documentation/devicetree/bindings/display/panel/lvds.yaml. > > > > lvds.yaml metions slot. 'bits_per_lane_and_dclk_cycle' means > > > > the > > > > number of slots. But, I don't find the word 'slot' in my lvds > > > > relevant > > > > specs which mentioned in lvds.yaml, so 'slots' is probably not > > > > a > > > > generic name(lvds.yaml is for display panel). So, I use > > > > 'bits_per_lane_and_dclk_cycle' as the name tells what it means. > > > > > > variable name is fine, explanation for bit per lane and > > > differential > > > clock cycle didnt help, maybe add better explanation of what this > > > variable means > > > > I may add an example diagram as below... > > Not really a diagram, you can add if you like.. But something which > explains in a sentence or few about the variable. Ok, no diagram. > > bits per lane per differential clock cycle ? Ok, will use this explaination. Regards, Liu Ying