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[2620:137:e000::1:20]) by mx.google.com with ESMTP id g9-20020a056a001a0900b004fb2ca5f6fcsi744779pfv.26.2022.04.14.12.16.57; Thu, 14 Apr 2022 12:17:13 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=qmFT8OJB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236238AbiDMOq4 (ORCPT + 99 others); Wed, 13 Apr 2022 10:46:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36878 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234503AbiDMOqy (ORCPT ); Wed, 13 Apr 2022 10:46:54 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0331913EB1; Wed, 13 Apr 2022 07:44:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649861071; x=1681397071; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=DxS3ZyjzkyOPLu53HmEj7fHH/b4qI5+E/iryReh3D7M=; b=qmFT8OJBBK3DmUtufYUFfWkHfhB+iJqyGhFPbYSDno+R8+ValBQSyPbZ Cd1dm8WNBPgoP+GD+r5J/wI5FotO7IjRhNHGripo5XnGdXJn7hglzfkA2 Nh96T1kSJXsgWvka8wnvtwPAGZgwG4n9/FbhaSCC3DrGPHbx6DJwv7R+X Q=; Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-02.qualcomm.com with ESMTP; 13 Apr 2022 07:44:30 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-SD-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2022 07:44:30 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 13 Apr 2022 07:44:29 -0700 Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 13 Apr 2022 07:44:25 -0700 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , CC: Srinivasa Rao Mandadapu , "Venkata Prasad Potturu" Subject: [PATCH v9 1/2] arm64: dts: qcom: sc7280: Add pinmux for I2S speaker and Headset Date: Wed, 13 Apr 2022 20:14:06 +0530 Message-ID: <1649861047-7811-2-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649861047-7811-1-git-send-email-quic_srivasam@quicinc.com> References: <1649861047-7811-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add pinmux nodes for primary and secondary I2S for SC7280 based platforms. Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Venkata Prasad Potturu Signed-off-by: Venkata Prasad Potturu --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 14 +++++++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 40 ++++++++++++++++++++++++++++++++ 2 files changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index ecbf2b8..1fc94b5 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -359,6 +359,20 @@ bias-disable; }; +&mi2s1_data0 { + drive-strength = <6>; + bias-disable; +}; + +&mi2s1_sclk { + drive-strength = <6>; + bias-disable; +}; + +&mi2s1_ws { + drive-strength = <6>; +}; + &pm7325_gpios { key_vol_up_default: key-vol-up-default { pins = "gpio6"; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index f0b64be..6e6cfeda 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3522,6 +3522,46 @@ function = "edp_hot"; }; + mi2s0_data0: mi2s0-data0 { + pins = "gpio98"; + function = "mi2s0_data0"; + }; + + mi2s0_data1: mi2s0-data1 { + pins = "gpio99"; + function = "mi2s0_data1"; + }; + + mi2s0_mclk: mi2s0-mclk { + pins = "gpio96"; + function = "pri_mi2s"; + }; + + mi2s0_sclk: mi2s0-sclk { + pins = "gpio97"; + function = "mi2s0_sck"; + }; + + mi2s0_ws: mi2s0-ws { + pins = "gpio100"; + function = "mi2s0_ws"; + }; + + mi2s1_data0: mi2s1-data0 { + pins = "gpio107"; + function = "mi2s1_data0"; + }; + + mi2s1_sclk: mi2s1-sclk { + pins = "gpio106"; + function = "mi2s1_sck"; + }; + + mi2s1_ws: mi2s1-ws { + pins = "gpio108"; + function = "mi2s1_ws"; + }; + pcie1_clkreq_n: pcie1-clkreq-n { pins = "gpio79"; function = "pcie1_clkreqn"; -- 2.7.4