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Date:   Thu, 14 Apr 2022 14:27:30 -0500
From:   Bjorn Helgaas <helgaas@kernel.org>
To:     Li Yang <leoyang.li@nxp.com>
Cc:     Bjorn Helgaas <bhelgaas@google.com>,
        Hou Zhiqiang <Zhiqiang.Hou@nxp.com>,
        Rob Herring <robh@kernel.org>, linux-pci@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 1/4] dt-bindings: pci: layerscape-pci: Add a optional
 property big-endian
Message-ID: <20220414192730.GA763552@bhelgaas>
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On Fri, Mar 11, 2022 at 05:49:35PM -0600, Li Yang wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> This property is to indicate the endianness when accessing the
> PEX_LUT and PF register block, so if these registers are
> implemented in big-endian, specify this property.
> 
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
>  Documentation/devicetree/bindings/pci/layerscape-pci.txt | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> index f36efa73a470..215d2ee65c83 100644
> --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> @@ -40,6 +40,10 @@ Required properties:
>    of the data transferred from/to the IP block. This can avoid the software
>    cache flush/invalid actions, and improve the performance significantly.
>  
> +Optional properties:
> +- big-endian: If the PEX_LUT and PF register block is in big-endian, specify
> +  this property.

What's the purpose of this?  I don't see any code that uses this
property.

I guess this might be related to of_device_is_big_endian()?  I do see
some code that uses of_device_is_big_endian(), but nothing that looks
relevant to layerscape in particular.

>  Example:
>  
>  	pcie@3400000 {
> -- 
> 2.25.1
>