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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DU2PR04MB8949.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 40107011-84d2-4a61-3ab6-08da1d7cdd3a X-MS-Exchange-CrossTenant-originalarrivaltime: 13 Apr 2022 18:38:54.9671 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Dmf8RLHn1AXHnL1KtBxetlw/76gzFd8MfWMFLkulqNYJp8i0V/G7YZz2hl8bGDrniyJegbHZ78iei4IGE+QBuA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR0402MB3335 X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RDNS_NONE,SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: Vladimir Oltean > Sent: Wednesday, April 13, 2022 1:22 PM > To: Leo Li > Cc: Z.Q. Hou ; Shawn Guo > ; linux-arm-kernel@lists.infradead.org; linux- > kernel@vger.kernel.org; Xiaowei Bao > Subject: Re: [PATCH v3 1/8] arm64: dts: ls1028a: Add PCIe EP nodes >=20 > On Wed, Apr 13, 2022 at 06:03:37PM +0000, Leo Li wrote: > > > arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi:631.23-656.5: Warning > > > (unique_unit_address): /soc/pcie@3400000: duplicate unit-address > > > (also used in node /soc/pcie-ep@3400000) > > > arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi:670.23-695.5: Warning > > > (unique_unit_address): /soc/pcie@3500000: duplicate unit-address > > > (also used in node /soc/pcie-ep@3500000) > > > > This would be a common problem for all the layerscape PCIe controller. > > The controller can either work in RC mode or EP mode. The current > > binding of the controller defined two compatibles, one for RC and one > > for EP. Therefore the SoC dtsi will have two nodes with the same unit > > address one for EP one for RC. Fixing this probably requires > > comprehensive updates to the binding which breaks backward > > compatibility. >=20 > So we have to live with these warnings forever now? >=20 > How are the PCIe controllers configured for RC or EP mode? Via RCW? > Is dynamic configuration possible? Yes. It is configured via RCW on reset. I don't think it can be changed at= runtime. >=20 > Can't U-Boot detect the operating mode from the RCW and fix up the > compatible string in case the controller is in endpoint mode? I believe the u-boot is already updating the node status to enable the corr= ect one. But it might be confusing to change the compatible and a bunch of= other properties at boot time. Regards, Leo