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[23.128.96.19]) by mx.google.com with ESMTPS id l1-20020a656801000000b003823f33adb2si2849706pgt.815.2022.04.15.18.28.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Apr 2022 18:28:09 -0700 (PDT) Received-SPF: softfail (google.com: domain of transitioning linux-kernel-owner@vger.kernel.org does not designate 23.128.96.19 as permitted sender) client-ip=23.128.96.19; Authentication-Results: mx.google.com; spf=softfail (google.com: domain of transitioning linux-kernel-owner@vger.kernel.org does not designate 23.128.96.19 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=alibaba.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id B007D143445; Fri, 15 Apr 2022 17:58:54 -0700 (PDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348681AbiDOC2N (ORCPT + 99 others); Thu, 14 Apr 2022 22:28:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34212 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344697AbiDOC2M (ORCPT ); Thu, 14 Apr 2022 22:28:12 -0400 Received: from out199-1.us.a.mail.aliyun.com (out199-1.us.a.mail.aliyun.com [47.90.199.1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 35B8685967; Thu, 14 Apr 2022 19:25:44 -0700 (PDT) X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R131e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=e01e04395;MF=tianjia.zhang@linux.alibaba.com;NM=1;PH=DS;RN=18;SR=0;TI=SMTPD_---0VA5Fc8T_1649989538; Received: from 30.240.101.97(mailfrom:tianjia.zhang@linux.alibaba.com fp:SMTPD_---0VA5Fc8T_1649989538) by smtp.aliyun-inc.com(127.0.0.1); Fri, 15 Apr 2022 10:25:40 +0800 Message-ID: Date: Fri, 15 Apr 2022 10:25:33 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH] arm64/sme: Add hwcap for Scalable Matrix Extension Content-Language: en-US To: Mark Brown Cc: Will Deacon , Catalin Marinas , Jonathan Corbet , Marc Zyngier , Joey Gouly , Vincenzo Frascino , Arnd Bergmann , Anshuman Khandual , Fuad Tabba , Mark Rutland , Vladimir Murzin , James Morse , Suzuki K Poulose , Mathieu Poirier , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org References: <20220414115544.36204-1-tianjia.zhang@linux.alibaba.com> From: Tianjia Zhang In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-5.7 required=5.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,NICE_REPLY_A, RDNS_NONE,SPF_HELO_NONE,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Mark, On 4/14/22 8:02 PM, Mark Brown wrote: > On Thu, Apr 14, 2022 at 07:55:44PM +0800, Tianjia Zhang wrote: > >> Allow userspace to detect support for SME (Scalable Matrix Extension) >> by providing a hwcap for it, using the official feature name FEAT_SME, >> declared in ARM DDI 0487H.a specification. > > There's already a hwcap for the core feature and all the subfeatures > added as part of the series I've been posting for SME: > > https://lore.kernel.org/linux-arm-kernel/20220408114328.1401034-1-broonie@kernel.org/ > > Why add something independently, especially given that there is no way > for userspace to do anything constructive with the feature without the > rest of the kernel support? Any attempt to use SME instructions without > kernel support will trap and generate a SIGILL even if the feature is > present in hardware. Great job, I encountered the issue of invalid REVD (requires FEAT_SME) instruction when developing SVE2 programs, so I plan to gradually support SME in the kernel, thanks for your contribution, you can ignore my patch. In addition, I would like to ask a question, whether there is an alternative SVE2 instruction for the REVD instruction that can complete this operation, if the machine does not support SME. > > Do you have a system with SME that you're trying to use? Review/testing > on the current series would be appreciated. Unfortunately, the value currently read by my machine ID_AA64PFR1_EL1 register is 0x121. It seems that the hardware does not support SME. Is there any other help I can provide? Kind regards, Tianjia