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In-Reply-To: <eadc4422-15bb-0b46-8235-db6e160e8d32@collabora.com>
From:   Peter Geis <pgwipeout@gmail.com>
Date:   Sat, 16 Apr 2022 06:17:15 -0400
Message-ID: <CAMdYzYq=nQhwY_4+Y=PM9do_Dcrg1pD-jeD=q36D48ks=WDVgw@mail.gmail.com>
Subject: Re: [PATCH v6 3/4] arm64: dts: rockchip: add rk3568 pcie2x1 controller
To:     Dmitry Osipenko <dmitry.osipenko@collabora.com>
Cc:     Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzk+dt@kernel.org>,
        Heiko Stuebner <heiko@sntech.de>,
        "open list:ARM/Rockchip SoC..." <linux-rockchip@lists.infradead.org>,
        PCI <linux-pci@vger.kernel.org>,
        devicetree <devicetree@vger.kernel.org>,
        arm-mail-list <linux-arm-kernel@lists.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
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On Sat, Apr 16, 2022 at 6:08 AM Dmitry Osipenko
<dmitry.osipenko@collabora.com> wrote:
>
> Hi Peter,
>
> On 4/16/22 13:05, Peter Geis wrote:
> > +     pcie2x1: pcie@fe260000 {
> > +             compatible = "rockchip,rk3568-pcie";
> > +             #address-cells = <3>;
> > +             #size-cells = <2>;
> > +             bus-range = <0x0 0xf>;
> > +             assigned-clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
> > +                      <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
> > +                      <&cru CLK_PCIE20_AUX_NDFT>;
>
> Why these assigned-clocks are needed? I don't see anything assigned in
> this patchset.

Ah, those are remnants of early bringup when performance wasn't good
and I was manually setting clock rates.