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Message-ID: <a8bb3ef6-8f37-709f-adfe-3608e5c1e11f@collabora.com>
Date:   Mon, 18 Apr 2022 01:23:28 +0300
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Subject: Re: [PATCH v6 3/4] arm64: dts: rockchip: add rk3568 pcie2x1
 controller
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To:     Peter Geis <pgwipeout@gmail.com>
Cc:     Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzk+dt@kernel.org>,
        Heiko Stuebner <heiko@sntech.de>,
        "open list:ARM/Rockchip SoC..." <linux-rockchip@lists.infradead.org>,
        PCI <linux-pci@vger.kernel.org>,
        devicetree <devicetree@vger.kernel.org>,
        arm-mail-list <linux-arm-kernel@lists.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
References: <20220416100502.627289-1-pgwipeout@gmail.com>
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 <CAMdYzYq=nQhwY_4+Y=PM9do_Dcrg1pD-jeD=q36D48ks=WDVgw@mail.gmail.com>
From:   Dmitry Osipenko <dmitry.osipenko@collabora.com>
In-Reply-To: <CAMdYzYq=nQhwY_4+Y=PM9do_Dcrg1pD-jeD=q36D48ks=WDVgw@mail.gmail.com>
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On 4/16/22 13:17, Peter Geis wrote:
> On Sat, Apr 16, 2022 at 6:08 AM Dmitry Osipenko
> <dmitry.osipenko@collabora.com> wrote:
>>
>> Hi Peter,
>>
>> On 4/16/22 13:05, Peter Geis wrote:
>>> +     pcie2x1: pcie@fe260000 {
>>> +             compatible = "rockchip,rk3568-pcie";
>>> +             #address-cells = <3>;
>>> +             #size-cells = <2>;
>>> +             bus-range = <0x0 0xf>;
>>> +             assigned-clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
>>> +                      <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
>>> +                      <&cru CLK_PCIE20_AUX_NDFT>;
>>
>> Why these assigned-clocks are needed? I don't see anything assigned in
>> this patchset.
> 
> Ah, those are remnants of early bringup when performance wasn't good
> and I was manually setting clock rates.

If it's not needed, should it be removed then? Otherwise it looks like
something is missing in the DT in regards to the assigned clocks.