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Date:   Mon, 18 Apr 2022 13:34:00 +0100
Message-ID: <87sfqaa7uv.wl-maz@kernel.org>
From:   Marc Zyngier <maz@kernel.org>
To:     Peter Geis <pgwipeout@gmail.com>
Cc:     Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
        Rob Herring <robh@kernel.org>,
        Krzysztof =?UTF-8?B?V2lsY3p5xYRza2k=?= <kw@linux.com>,
        Bjorn Helgaas <bhelgaas@google.com>,
        Heiko Stuebner <heiko@sntech.de>,
        "open list:ARM/Rockchip SoC..." <linux-rockchip@lists.infradead.org>,
        PCI <linux-pci@vger.kernel.org>,
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        arm-mail-list <linux-arm-kernel@lists.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v7 2/4] PCI: dwc: rockchip: add legacy interrupt support
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On Mon, 18 Apr 2022 12:37:00 +0100,
Peter Geis <pgwipeout@gmail.com> wrote:
> 
> On Sun, Apr 17, 2022 at 5:53 AM Marc Zyngier <maz@kernel.org> wrote:
> >
> > On Sat, 16 Apr 2022 14:24:26 +0100,
> > Peter Geis <pgwipeout@gmail.com> wrote:
> > >
> > > Okay, that makes sense. I'm hitting the entire block when it should be
> > > the individual IRQ.
> > > I also notice some drivers protect this with a spinlock while others
> > > do not, how should this be handled?
> >
> > It obviously depends on how the HW. works. If this is a shared
> > register using a RMW sequence, then you need some form of mutual
> > exclusion in order to preserve the atomicity of the update.
> >
> > If the HW supports updating the masks using a set of hot bits (with
> > separate clear/set registers), than there is no need for locking.  In
> > your case PCIE_CLIENT_INTR_MASK_LEGACY seems to support this odd
> > "write-enable" feature which can probably be used to implement a
> > lockless access, something like:
> >
> >         void mask(struct irq_data *d)
> >         {
> >                 u32 val = BIT(d->hwirq + 16) | BIT(d->hwirq);
> 
> This is what HIWORD_UPDATE_BIT does, it's rather common in Rockchip code.
> I believe I can safely drop the spinlock when enabling/disabling
> individual interrupts.

Yes.

> 
> >                 writel_relaxed(val, ...);
> >         }
> >
> >         void mask(struct irq_data *d)
> >         {
> >                 u32 val = BIT(d->hwirq + 16);
> >                 writel_relaxed(val, ...);
> >         }
> >
> > Another thing is that it is completely unclear to me what initialises
> > these interrupts the first place (INTR_MASK_LEGACY, INTR_EN_LEGACY).
> > Are you relying on the firmware to do that for you?
> 
> There is no dedicated mask or enable/disable for the legacy interrupt
> line (unless it's undocumented).

I'm talking about the INTR_MASK_LEGACY and INTR_EN_LEGACY registers,
which control the INTx (although the latter seems to default to some
reserved values). I don't see where you initialise them to a state
where they are enabled and masked, which should be the initial state
once this driver has probed. The output interrupt itself is obviously
controlled by the GIC driver.

> It appears to be enabled via an "or" function with the emulated interrupts.
> As far as I can tell this is common for dw-pcie, looking at the other drivers.

I think we're talking past each other. I'm solely concerned with the
initialisation of the input control registers, for which I see no code
in this patch.

	M.

-- 
Without deviation from the norm, progress is not possible.