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Subject: Re: [PATCH v2 6/8] ARM: dts: r9a06g032: Add internal PCI bridge node
To:     Herve Codina <herve.codina@bootlin.com>,
        Marek Vasut <marek.vasut+renesas@gmail.com>,
        Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>,
        Bjorn Helgaas <bhelgaas@google.com>,
        "Rob Herring" <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzk+dt@kernel.org>,
        Geert Uytterhoeven <geert+renesas@glider.be>,
        Magnus Damm <magnus.damm@gmail.com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
        =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= <kw@linux.com>
CC:     Rob Herring <robh@kernel.org>, <linux-pci@vger.kernel.org>,
        <linux-renesas-soc@vger.kernel.org>, <devicetree@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>,
        Sergey Shtylyov <s.shtylyov@omp.ru>,
        "Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
        Clement Leger <clement.leger@bootlin.com>,
        Miquel Raynal <miquel.raynal@bootlin.com>
References: <20220414074011.500533-1-herve.codina@bootlin.com>
 <20220414074011.500533-7-herve.codina@bootlin.com>
From:   Sergey Shtylyov <s.shtylyov@omp.ru>
Organization: Open Mobile Platform
Message-ID: <05c96b4d-313b-1aad-0ee5-61e54672765e@omp.ru>
Date:   Mon, 18 Apr 2022 12:02:52 +0300
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Hello!

On 4/14/22 10:40 AM, Herve Codina wrote:

> Add the device node for the r9a06g032 internal PCI bridge device.
> 
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> ---
>  arch/arm/boot/dts/r9a06g032.dtsi | 28 ++++++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
> index 636a6ab31c58..848dc034bb8c 100644
> --- a/arch/arm/boot/dts/r9a06g032.dtsi
> +++ b/arch/arm/boot/dts/r9a06g032.dtsi
> @@ -211,6 +211,34 @@ gic: interrupt-controller@44101000 {
>  			interrupts =
>  				<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
>  		};
> +
> +		pci_usb: pci@40030000 {
> +			compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1";
> +			device_type = "pci";
> +			clocks = <&sysctrl R9A06G032_HCLK_USBH>,
> +				 <&sysctrl R9A06G032_HCLK_USBPM>,
> +				 <&sysctrl R9A06G032_CLK_PCI_USB>;
> +			clock-names = "hclk_usbh", "hclk_usbpm", "clk_pci_usb";
> +			reg = <0x40030000 0xc00>,
> +			      <0x40020000 0x1100>;
> +			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
> +			status = "disabled";
> +
> +			bus-range = <0 0>;
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +			#interrupt-cells = <1>;

   Really? I don't think this PCI bridge is also an interrupt controller...

> +			ranges = <0x02000000 0 0x40020000 0x40020000 0 0x00010000>;
> +			/* Should map all possible DDR as inbound ranges, but
> +			 * the IP only supports a 256MB, 512MB, or 1GB window.
> +			 * flags, PCI addr (64-bit), CPU addr, PCI size (64-bit)
> +			 */
> +			dma-ranges = <0x42000000 0 0x80000000 0x80000000 0 0x40000000>;
> +			interrupt-map-mask = <0xf800 0 0 0x7>;
> +			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
> +					 0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
> +					 0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
> +		};
>  	};
>  
>  	timer {

MBR, Sergey