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Message-ID: <19948f89-80fe-a726-2a03-db16bf5d66ef@intel.com>
Date:   Tue, 19 Apr 2022 14:45:30 +0300
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Subject: Re: [RESEND, PATCH] mmc: sdhci-pci-gli: A workaround to allow GL9755
 to enter ASPM L1.2
Content-Language: en-US
To:     Ben Chuang <benchuanggli@gmail.com>, ulf.hansson@linaro.org
Cc:     SeanHY.Chen@genesyslogic.com.tw, ben.chuang@genesyslogic.com.tw,
        greg.tu@genesyslogic.com.tw, linux-kernel@vger.kernel.org,
        linux-mmc@vger.kernel.org
References: <20220414094945.457500-1-benchuanggli@gmail.com>
From:   Adrian Hunter <adrian.hunter@intel.com>
Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki,
 Business Identity Code: 0357606 - 4, Domiciled in Helsinki
In-Reply-To: <20220414094945.457500-1-benchuanggli@gmail.com>
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On 14/04/22 12:49, Ben Chuang wrote:
> From: Ben Chuang <ben.chuang@genesyslogic.com.tw>
> 
> When GL9755 enters ASPM L1 sub-states, it will stay at L1.1 and will not
> enter L1.2. The workaround is to toggle PM state to allow GL9755 to enter
> ASPM L1.2.
> 
> Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>

Acked-by: Adrian Hunter <adrian.hunter@intel.com>

> ---
>  drivers/mmc/host/sdhci-pci-gli.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
> index 97035d77c18c..52230857388f 100644
> --- a/drivers/mmc/host/sdhci-pci-gli.c
> +++ b/drivers/mmc/host/sdhci-pci-gli.c
> @@ -137,6 +137,9 @@
>  #define PCI_GLI_9755_SerDes  0x70
>  #define PCI_GLI_9755_SCP_DIS   BIT(19)
>  
> +#define PCI_GLI_9755_PM_CTRL     0xFC
> +#define   PCI_GLI_9755_PM_STATE    GENMASK(1, 0)
> +
>  #define GLI_MAX_TUNING_LOOP 40
>  
>  /* Genesys Logic chipset */
> @@ -597,6 +600,13 @@ static void gl9755_hw_setting(struct sdhci_pci_slot *slot)
>  			    GLI_9755_CFG2_L1DLY_VALUE);
>  	pci_write_config_dword(pdev, PCI_GLI_9755_CFG2, value);
>  
> +	/* toggle PM state to allow GL9755 to enter ASPM L1.2 */
> +	pci_read_config_dword(pdev, PCI_GLI_9755_PM_CTRL, &value);
> +	value |= PCI_GLI_9755_PM_STATE;
> +	pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
> +	value &= ~PCI_GLI_9755_PM_STATE;
> +	pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
> +
>  	gl9755_wt_off(pdev);
>  }
>