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Date:   Tue, 19 Apr 2022 01:41:37 +0200
From:   Andrea Parri <parri.andrea@gmail.com>
To:     Guo Ren <guoren@kernel.org>
Cc:     Boqun Feng <boqun.feng@gmail.com>,
        Daniel Lustig <dlustig@nvidia.com>,
        "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>,
        Arnd Bergmann <arnd@arndb.de>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Mark Rutland <mark.rutland@arm.com>,
        Will Deacon <will@kernel.org>,
        Peter Zijlstra <peterz@infradead.org>,
        linux-arch <linux-arch@vger.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        linux-riscv <linux-riscv@lists.infradead.org>,
        Guo Ren <guoren@linux.alibaba.com>
Subject: Re: [PATCH V2 0/3] riscv: atomic: Optimize AMO instructions usage
Message-ID: <20220418234137.GA444607@anparri>
References: <20220412034957.1481088-1-guoren@kernel.org>
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> > Seems to me that you are basically reverting 5ce6c1f3535f
> > ("riscv/atomic: Strengthen implementations with fences"). That commit
> > fixed an memory ordering issue, could you explain why the issue no
> > longer needs a fix?
> 
> I'm not reverting the prior patch, just optimizing it.
> 
> In RISC-V “A” Standard Extension for Atomic Instructions spec, it said:

With reference to the RISC-V herd specification at:

  https://github.com/riscv/riscv-isa-manual.git

the issue, better, lr-sc-aqrl-pair-vs-full-barrier seems to _no longer_
need a fix since commit:

  03a5e722fc0f ("Updates to the memory consistency model spec")

(here a template, to double check:

  https://github.com/litmus-tests/litmus-tests-riscv/blob/master/tests/non-mixed-size/HAND/LR-SC-NOT-FENCE.litmus )

I defer to Daniel/others for a "bi-section" of the prose specification.
;-)

  Andrea