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Message-ID: <62bbc2a6-92fb-ff2b-a43f-ecb402e8f90c@kernel.org>
Date:   Tue, 19 Apr 2022 09:11:09 +0200
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Subject: Re: [PATCH 3/5] PCI: axis: Add ARTPEC-8 PCIe controller driver
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To:     wangseok.lee@samsung.com, robh+dt <robh+dt@kernel.org>,
        krzk+dt <krzk+dt@kernel.org>, kishon <kishon@ti.com>,
        vkoul <vkoul@kernel.org>,
        linux-kernel <linux-kernel@vger.kernel.org>,
        "jesper.nilsson" <jesper.nilsson@axis.com>,
        "lars.persson" <lars.persson@axis.com>
Cc:     bhelgaas <bhelgaas@google.com>,
        linux-phy <linux-phy@lists.infradead.org>,
        linux-pci <linux-pci@vger.kernel.org>,
        devicetree <devicetree@vger.kernel.org>,
        "lorenzo.pieralisi" <lorenzo.pieralisi@arm.com>, kw <kw@linux.com>,
        linux-arm-kernel <linux-arm-kernel@axis.com>,
        kernel <kernel@axis.com>, Moon-Ki Jun <moonki.jun@samsung.com>,
        Dongjin Yang <dj76.yang@samsung.com>
References: <CGME20220419000730epcms2p77c94d5e55db13ebf2f88b25d16b6ef7a@epcms2p7>
 <20220419000730epcms2p77c94d5e55db13ebf2f88b25d16b6ef7a@epcms2p7>
From:   Krzysztof Kozlowski <krzk@kernel.org>
In-Reply-To: <20220419000730epcms2p77c94d5e55db13ebf2f88b25d16b6ef7a@epcms2p7>
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Precedence: bulk

On 19/04/2022 02:07, Wangseok Lee wrote:
>> On 28/03/2022 04:14, 이왕석 wrote:
>>>  Add support Axis, ARTPEC-8 SoC.
>>>  ARTPEC-8 is the SoC platform of Axis Communications.
>>>  This is based on arm64 and support GEN4 & 2lane.
>>>  This PCIe controller is based on DesignWare Hardware core
>>>  and uses DesignWare core functions to implement the driver.
>>>  This is based on driver/pci/controller/dwc/pci-exynos.c
>>>  
>>>  Signed-off-by: Wangseok Lee 
>>> ---
>>>  drivers/pci/controller/dwc/Kconfig        |  31 +
>>>  drivers/pci/controller/dwc/Makefile       |   1 +
>>>  drivers/pci/controller/dwc/pcie-artpec8.c | 912 ++++++++++++++++++++++++++++++
>>>  3 files changed, 944 insertions(+)
>>>  create mode 100644 drivers/pci/controller/dwc/pcie-artpec8.c
>>>
>>
>> I took a look at the your driver and at existing PCIe Exynos driver.
>> Unfortunately PCIe Exynos driver is in poor shape, really poor. This
>> would explain that maybe it's better to have new driver instead of
>> merging them, especially that hardware is different. Although I am still
>> waiting for some description of these differences...
>>
>> I said that Exynos PCIe looks poor... but what is worse, it looks like
>> you based on it so you copied or some bad patterns it had.
>>
>> Except this the driver has several coding style issues, so please be
>> sure to run checkpatch, sparse and smatch before sending it.
>>
>> Please work on this driver to make it close to Linux coding style, so
>> there will be no need for us, reviewers, focus on basic stuff.
>>
>> Optionally, send all this to staging. :)
>>
>> Best regards,
>> Krzysztof
> Hi,
> 
> Thank you for your kindness review.
> I will re-work again close to the linux coding style.
> Addiltionaly, If you tell me what "bad patterns" you mentioned,
> it will be very helpful for the work.
> Could you please tell me that?

Except the tools I mentioned before, the patterns are:
1. debug messages for probe or other functions (we have ftrace and other
tools for that).
2. Inconsistent coding style (e.g. different indentation in structure
members).
3. Inconsistent code (e.g. artpec8_pcie_get_subsystem_resources() gets
device from pdev and from pci so you have two same pointers; or
artpec8_pcie_get_ep_mem_resources() stores dev as local variable but
uses instead pdev->dev).
4. Not using devm_platform_ioremap_resource().
5. Wrappers over writel() and readl() which do nothing else than wrap
one function.
6. Printing messages in interrupt handlers.
7. Several local/static structures or array are not const. Plus they are
defined all through the code, instead of beginning of a file.

Also - you have four clocks, so use clk bulk API.


Best regards,
Krzysztof