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[188.155.176.92]) by smtp.gmail.com with ESMTPSA id u6-20020a17090626c600b006e74ef7f092sm6012164ejc.176.2022.04.19.12.40.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 19 Apr 2022 12:40:25 -0700 (PDT) Message-ID: <8b9ad0a6-acc0-aad9-c49d-e4a4b38374bb@linaro.org> Date: Tue, 19 Apr 2022 21:40:24 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: Aw: Re: [RFC/RFT 2/6] dt-bindings: soc: grf: add pcie30-{phy,pipe}-grf Content-Language: en-US To: Frank Wunderlich Cc: Frank Wunderlich , linux-rockchip@lists.infradead.org, Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Bjorn Helgaas , Philipp Zabel , Johan Jonker , Peter Geis , Michael Riesch , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org References: <20220416135458.104048-1-linux@fw-web.de> <20220416135458.104048-3-linux@fw-web.de> <02b3fe1c-12f9-8f96-a9b5-df44ca001825@linaro.org> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 19/04/2022 19:29, Frank Wunderlich wrote: >> Gesendet: Montag, 18. April 2022 um 17:54 Uhr >> Von: "Krzysztof Kozlowski" > >>> --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml >>> +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml >>> @@ -14,6 +14,8 @@ properties: >>> oneOf: >>> - items: >>> - enum: >>> + - rockchip,pcie30-phy-grf >>> + - rockchip,pcie30-pipe-grf >> >> These are without SoC parts. Are these PCIe v3 General Register Files >> part of some PCIe spec? > > imho they are shared across SoCs rk3568 and rk3588, but have only seen rk3568 implementation yet. > PCIe driver currently supports these 2 Soc (different offsets in the Phy-GRF), but can only test rk3568. > > pipe-grf seems only be used for rk35688 (offset used in probe is defined for this SoC), which i cannot test. > > so i have left them SoC independed. Compatibles should be SoC dependent, with some exceptions. Lack of documentation or lack of possibility of testing is actually argument against any exception, so they should be SoC specific/dependent. Best regards, Krzysztof